CTCaer 73a133556d bdk: sdram: correct sku related info ...

Validated so rename accordingly.

2023-06-08 02:57:30 +03:00

..

emc.h

sdram: Add T210B01 support & new LPDDR4X tables

2020-06-26 18:53:12 +03:00

heap.c

bdk: whitespace refactor

2022-07-11 22:10:11 +03:00

heap.h

bdk: mem: improve emc MRR reading

2022-10-11 03:51:12 +03:00

mc_t210.h

bdk: mem: improve emc MRR reading

2022-10-11 03:51:12 +03:00

mc.c

bdk: migrate timers/sleeps to timer driver

2022-06-27 10:22:19 +03:00

mc.h

bdk: mc: always on ahb arbitration

2022-01-29 01:29:02 +02:00

minerva.c

bdk: mem: minerva: check table size in clock check

2023-06-08 02:45:34 +03:00

minerva.h

bdk: sdmmc: increase bw priority to SDMMC1 for L4T

2023-04-06 17:30:01 +03:00

mtc_table.h

Utilize hekate's BDK for hekate main and Nyx

2020-06-14 16:45:45 +03:00

sdram_config_t210b01.inl

bdk: sdram: name 2 of the new ram chips

2023-06-08 02:52:03 +03:00

sdram_config.inl

bdk: migrate timers/sleeps to timer driver

2022-06-27 10:22:19 +03:00

sdram_lp0_param_t210.h

sc7: Add T210B01 SC7/LP0 (deep sleep) support

2020-06-26 19:00:30 +03:00

sdram_lp0_param_t210b01.h

sc7: Add T210B01 SC7/LP0 (deep sleep) support

2020-06-26 19:00:30 +03:00

sdram_lp0.c

sdram: fix building for embedded lp0 config

2021-09-17 23:17:56 +03:00

sdram_param_t210.h

sdram: Add T210B01 support & new LPDDR4X tables

2020-06-26 18:53:12 +03:00

sdram_param_t210b01.h

sdram: Add T210B01 support & new LPDDR4X tables

2020-06-26 18:53:12 +03:00

sdram.c

bdk: sdram: name 2 of the new ram chips

2023-06-08 02:52:03 +03:00

sdram.h

bdk: sdram: correct sku related info

2023-06-08 02:57:30 +03:00

smmu.c

bdk: whitespace refactor

2022-07-11 22:10:11 +03:00

smmu.h

bdk: various functionality independent changes

2022-01-16 01:03:24 +02:00