forked from CTCaer/hekate
bdk: mem: minerva: check table size in clock check
Don't hardcode table size to 10.
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bc0eea11f3
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@ -38,7 +38,7 @@ void (*minerva_cfg)(mtc_config_t *mtc_cfg, void *);
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u32 minerva_init()
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{
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u32 curr_ram_idx = 0;
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u32 tbl_idx = 0;
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minerva_cfg = NULL;
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mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
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@ -103,13 +103,13 @@ u32 minerva_init()
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// Get current frequency
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u32 current_emc_clk_src = CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC);
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for (curr_ram_idx = 0; curr_ram_idx < 10; curr_ram_idx++)
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for (tbl_idx = 0; tbl_idx < mtc_cfg->table_entries; tbl_idx++)
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{
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if (current_emc_clk_src == mtc_cfg->mtc_table[curr_ram_idx].clk_src_emc)
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if (current_emc_clk_src == mtc_cfg->mtc_table[tbl_idx].clk_src_emc)
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break;
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}
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mtc_cfg->rate_from = mtc_cfg->mtc_table[curr_ram_idx].rate_khz;
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mtc_cfg->rate_from = mtc_cfg->mtc_table[tbl_idx].rate_khz;
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mtc_cfg->rate_to = FREQ_204;
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mtc_cfg->train_mode = OP_TRAIN;
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minerva_cfg(mtc_cfg, NULL);
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