forked from CTCaer/hekate
57c8fd1f8c
`BDK_WATCHDOG_FIQ_ENABLE` enables watchdog handling. `BDK_RESTART_BL_ON_WDT` causes a reload of bootloader on FIQ These 2 are useful when wanting to detect and handle hangs.
240 lines
7.1 KiB
ArmAsm
240 lines
7.1 KiB
ArmAsm
/*
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* Copyright (c) 2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Armv7tdmi Status register.
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*
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* bit0: Mode 0.
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* bit1: Mode 1.
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* bit2: Mode 2.
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* bit3: Mode 3.
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* bit4: Mode 4.
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* bit5: Thumb state.
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* bit6: FIQ disable.
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* bit7: IRQ disable.
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* bit8-27: Reserved.
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* bit28: Overflow condition.
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* bit29: Carry/Borrow/Extend condition.
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* bit30: Zero condition.
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* bit31: Negative/Less than condition.
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*
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* M[4:0] | Mode | Visible Thumb-state registers | Visible ARM-state registers
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* 10000 | USER | r0–r7, SP, LR, PC, CPSR | r0–r14, PC, CPSR
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* 10001 | FIQ | r0–r7, SP_fiq, LR_fiq, PC, CPSR, SPSR_fiq | r0–r7, r8_fiq–r14_fiq, PC, CPSR, SPSR_fiq
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* 10010 | IRQ | r0–r7, SP_irq, LR_irq, PC, CPSR, SPSR_irq | r0–r12, r13_irq, r14_irq, PC, CPSR, SPSR_irq
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* 10011 | SVC | r0–r7, SP_svc, LR_svc, PC, CPSR, SPSR_svc | r0–r12, r13_svc, r14_svc, PC, CPSR, SPSR_svc
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* 10111 | ABRT | r0–r7, SP_abt, LR_abt, PC, CPSR, SPSR_abt | r0–r12, r13_abt, r14_abt, PC, CPSR, SPSR_abt
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* 11011 | UNDF | r0–r7, SP_und, LR_und, PC, CPSR, SPSR_und | r0–r12, r13_und, r14_und, PC, CPSR, SPSR_und
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* 11111 | SYS | r0–r7, SP, LR, PC, CPSR | r0–r14, PC, CPSR
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*/
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#define EXCP_EN_ADDR 0x4003FFFC
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#define EXCP_TYPE_ADDR 0x4003FFF8
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#define EXCP_LR_ADDR 0x4003FFF4
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#define EXCP_VEC_BASE 0x6000F000
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#define EVP_COP_RESET_VECTOR 0x200
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#define EVP_COP_UNDEF_VECTOR 0x204
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#define EVP_COP_SWI_VECTOR 0x208
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#define EVP_COP_PREFETCH_ABORT_VECTOR 0x20C
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#define EVP_COP_DATA_ABORT_VECTOR 0x210
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#define EVP_COP_RSVD_VECTOR 0x214
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#define EVP_COP_IRQ_VECTOR 0x218
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#define EVP_COP_FIQ_VECTOR 0x21C
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#define MODE_USR 0x10
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#define MODE_FIQ 0x11
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#define MODE_IRQ 0x12
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#define MODE_SVC 0x13
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#define MODE_ABT 0x17
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#define MODE_UDF 0x1B
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#define MODE_SYS 0x1F
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#define MODE_MASK 0x1F
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#define FIQ 0x40
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#define IRQ 0x80
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.section .text._irq_setup
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.arm
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.extern ipl_main
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.type ipl_main, %function
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.extern svc_handler
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.type svc_handler, %function
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.extern irq_handler
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.type irq_handler, %function
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.extern fiq_setup
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.type fiq_setup, %function
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.extern fiq_handler
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.type fiq_handler, %function
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.globl _irq_setup
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.type _irq_setup, %function
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_irq_setup:
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MRS R0, CPSR
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BIC R0, R0, #MODE_MASK /* Clear mode bits */
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ORR R0, R0, #(MODE_SVC | IRQ | FIQ) /* SUPERVISOR mode, IRQ/FIQ disabled */
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MSR CPSR, R0
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/* Setup IRQ stack pointer */
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MSR CPSR, #(MODE_IRQ | IRQ | FIQ) /* IRQ mode, IRQ/FIQ disabled */
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LDR SP, =0x40040000
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/* Setup FIQ stack pointer */
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MSR CPSR, #(MODE_FIQ | IRQ | FIQ) /* FIQ mode, IRQ/FIQ disabled */
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LDR SP, =0x40040000
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/* Setup SYS stack pointer */
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MSR CPSR, #(MODE_SYS | IRQ | FIQ) /* SYSTEM mode, IRQ/FIQ disabled */
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LDR SP, =0x4003FF00 /* Will be changed later to DRAM */
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MOV LR, PC
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BL setup_vectors
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/*BL fiq_setup*/
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/* Enable interrupts */
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BL irq_enable_cpu_irq_exceptions
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B ipl_main
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B .
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.globl excp_reset
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.type excp_reset, %function
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excp_reset:
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LDR R0, =EXCP_EN_ADDR
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LDR R1, =0x30505645 /* EVP0 */
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STR R1, [R0] /* EVP0 in EXCP_EN_ADDR */
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LDR R0, =EXCP_LR_ADDR
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MOV R1, LR
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STR R1, [R0] /* Save LR in EXCP_LR_ADDR */
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LDR R0, =__bss_start
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EOR R1, R1, R1
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LDR R2, =__bss_end
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SUB R2, R2, R0
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BL memset
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B _irq_setup
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_reset_handler:
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LDR R0, =EXCP_TYPE_ADDR
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LDR R1, =0x545352 /* RST */
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STR R1, [R0] /* RST in EXCP_TYPE_ADDR */
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B excp_reset
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_undefined_handler:
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LDR R0, =EXCP_TYPE_ADDR
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LDR R1, =0x464455 /* UDF */
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STR R1, [R0] /* UDF in EXCP_TYPE_ADDR */
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B excp_reset
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_prefetch_abort_handler:
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LDR R0, =EXCP_TYPE_ADDR
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LDR R1, =0x54424150 /* PABT */
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STR R1, [R0] /* PABT in EXCP_TYPE_ADDR */
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B excp_reset
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_data_abort_handler:
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LDR R0, =EXCP_TYPE_ADDR
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LDR R1, =0x54424144 /* DABT */
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STR R1, [R0] /* DABT in EXCP_TYPE_ADDR */
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B excp_reset
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.globl irq_enable_cpu_irq_exceptions
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.type irq_enable_cpu_irq_exceptions, %function
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irq_enable_cpu_irq_exceptions:
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MRS R12, CPSR
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BIC R12, R12, #(IRQ | FIQ) /* IRQ/FIQ enabled */
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MSR CPSR, R12
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BX LR
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.globl irq_disable_cpu_irq_exceptions
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.type irq_disable_cpu_irq_exceptions, %function
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irq_disable_cpu_irq_exceptions:
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MRS R12, CPSR
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ORR R12, R12, #(IRQ | FIQ) /* IRQ/FIQ disabled */
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MSR CPSR, R12
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BX LR
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_irq_handler:
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MOV R13, R0 /* Save R0 in R13_IRQ */
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SUB R0, LR, #4 /* Put return address in R0_SYS */
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MOV LR, R1 /* Save R1 in R14_IRQ (LR) */
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MRS R1, SPSR /* Put the SPSR in R1_SYS */
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MSR CPSR_c, #(MODE_SYS | IRQ) /* SYSTEM mode, IRQ disabled */
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STMFD SP!, {R0, R1} /* SPSR and PC */
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STMFD SP!, {R2-R3, R12, LR} /* AAPCS-clobbered registers */
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MOV R0, SP /* Make SP_SYS visible to IRQ mode */
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SUB SP, SP, #8 /* Make room for stacking R0 and R1 */
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MSR CPSR_c, #(MODE_IRQ | IRQ) /* IRQ mode, IRQ disabled */
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STMFD R0!, {R13, R14} /* Finish saving the context (R0, R1) */
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MSR CPSR_c, #(MODE_SYS | IRQ) /* SYSTEM mode, IRQ disabled */
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LDR R12, =irq_handler
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MOV LR, PC /* Copy the return address to link register */
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BX R12 /* Call the C IRQ handler (ARM/THUMB) */
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MSR CPSR_c, #(MODE_SYS | IRQ | FIQ) /* SYSTEM mode, IRQ/FIQ disabled */
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MOV R0, SP /* Make SP_SYS visible to IRQ mode */
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ADD SP, SP, #32 /* Fake unstacking 8 registers from SP_SYS */
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MSR CPSR_c, #(MODE_IRQ | IRQ | FIQ) /* IRQ mode, IRQ/FIQ disabled */
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MOV SP, R0 /* Copy SP_SYS to SP_IRQ */
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LDR R0, [SP, #28] /* Load the saved SPSR from the stack */
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MSR SPSR_cxsf, R0 /* Copy it into SPSR_IRQ */
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LDMFD SP, {R0-R3, R12, LR}^ /* Unstack all saved USER/SYSTEM registers */
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NOP /* Cant access barked registers immediately */
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LDR LR, [SP, #24] /* Load return address from the SYS stack */
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MOVS PC, LR /* Return restoring CPSR from SPSR */
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_fiq_handler:
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BL fiq_handler
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setup_vectors:
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/* Setup vectors */
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LDR R0, =EXCP_VEC_BASE
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LDR R1, =_reset_handler
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STR R1, [R0, #EVP_COP_RESET_VECTOR]
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LDR R1, =_undefined_handler
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STR R1, [R0, #EVP_COP_UNDEF_VECTOR]
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LDR R1, =_reset_handler
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STR R1, [R0, #EVP_COP_SWI_VECTOR]
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LDR R1, =_prefetch_abort_handler
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STR R1, [R0, #EVP_COP_PREFETCH_ABORT_VECTOR]
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LDR R1, =_data_abort_handler
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STR R1, [R0, #EVP_COP_DATA_ABORT_VECTOR]
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LDR R1, =_reset_handler
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STR R1, [R0, #EVP_COP_RSVD_VECTOR]
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LDR R1, =_irq_handler
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STR R1, [R0, #EVP_COP_IRQ_VECTOR]
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LDR R1, =_fiq_handler
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STR R1, [R0, #EVP_COP_FIQ_VECTOR]
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BX LR
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