forked from CTCaer/hekate
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22
README.md
22
README.md
@ -188,20 +188,26 @@ hekate has a boot storage in the binary that helps it configure it outside of BP
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```
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hekate (c) 2018, naehrwert, st4rk.
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(c) 2018-2023, CTCaer.
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(c) 2018-2024, CTCaer.
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Nyx GUI (c) 2019-2023, CTCaer.
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Nyx GUI (c) 2019-2024, CTCaer.
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Thanks to: derrek, nedwill, plutoo, shuffle2, smea, thexyz, yellows8.
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Greetings to: fincs, hexkyz, SciresM, Shiny Quagsire, WinterMute.
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Open source and free packages used:
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- FatFs R0.13a, Copyright (c) 2017, ChaN
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- bcl-1.2.0, Copyright (c) 2003-2006, Marcus Geelnard
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- Atmosphère (Exosphere types/panic, prc id kernel patches),
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Copyright (c) 2018-2019, Atmosphère-NX
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- elfload, Copyright (c) 2014 Owen Shepherd, Copyright (c) 2018 M4xw
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- Littlev Graphics Library, Copyright (c) 2016 Gabor Kiss-Vamosi
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- Littlev Graphics Library,
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Copyright (c) 2016-2018 Gabor Kiss-Vamosi
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- FatFs R0.13c,
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Copyright (c) 2006-2018, ChaN
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Copyright (c) 2018-2022, CTCaer
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- bcl-1.2.0,
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Copyright (c) 2003-2006, Marcus Geelnard
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- blz,
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Copyright (c) 2018, SciresM
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- elfload,
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Copyright (c) 2014 Owen Shepherd,
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Copyright (c) 2018 M4xw
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___
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.-' `'.
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@ -1,11 +1,11 @@
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# IPL Version.
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BLVERSION_MAJOR := 6
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BLVERSION_MINOR := 1
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BLVERSION_HOTFX := 1
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BLVERSION_MINOR := 2
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BLVERSION_HOTFX := 0
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BLVERSION_RSVD := 0
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# Nyx Version.
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NYXVERSION_MAJOR := 1
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NYXVERSION_MINOR := 6
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NYXVERSION_HOTFX := 1
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NYXVERSION_HOTFX := 2
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NYXVERSION_RSVD := 0
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218
bdk/display/di.c
218
bdk/display/di.c
@ -59,7 +59,7 @@ void display_wait_interrupt(u32 intr)
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// Interrupts are masked. Poll status register for checking if fired.
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while (!(DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) & intr))
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;
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;
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}
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static void _display_dsi_wait(u32 timeout, u32 off, u32 mask)
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@ -373,24 +373,10 @@ void display_init()
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// Get Chip ID.
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bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210;
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// T210B01: Power on SD2 regulator for supplying LDO0.
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if (!tegra_t210)
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{
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// Set SD2 regulator voltage.
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max7762x_regulator_set_voltage(REGULATOR_SD2, 1325000);
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// Set slew rate and enable SD2 regulator.
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD2_CFG, (1 << MAX77620_SD_SR_SHIFT) | MAX77620_SD_CFG1_FSRADE_SD_ENABLE);
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max7762x_regulator_enable(REGULATOR_SD2, true);
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}
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// Enable LCD DVDD.
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// Enable DSI AVDD.
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max7762x_regulator_set_voltage(REGULATOR_LDO0, 1200000);
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max7762x_regulator_enable(REGULATOR_LDO0, true);
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if (tegra_t210)
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max77620_config_gpio(7, MAX77620_GPIO_OUTPUT_ENABLE); // T210: LD0 -> GPIO7 -> LCD.
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// Enable Display Interface specific clocks.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI);
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI);
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@ -448,26 +434,19 @@ void display_init()
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clock_enable_plld(3, 20, true, tegra_t210);
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// Setup Display Interface initial window configuration.
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exec_cfg((u32 *)DISPLAY_A_BASE, _di_dc_setup_win_config, CFG_SIZE(_di_dc_setup_win_config));
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reg_write_array((u32 *)DISPLAY_A_BASE, _di_dc_setup_win_config, ARRAY_SIZE(_di_dc_setup_win_config));
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// Setup dsi init sequence packets.
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exec_cfg((u32 *)DSI_BASE, _di_dsi_init_irq_pkt_config0, CFG_SIZE(_di_dsi_init_irq_pkt_config0));
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if (tegra_t210)
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DSI(_DSIREG(DSI_INIT_SEQ_DATA_15)) = 0;
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else
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DSI(_DSIREG(DSI_INIT_SEQ_DATA_15_B01)) = 0;
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exec_cfg((u32 *)DSI_BASE, _di_dsi_init_irq_pkt_config1, CFG_SIZE(_di_dsi_init_irq_pkt_config1));
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reg_write_array((u32 *)DSI_BASE, _di_dsi_init_config0, ARRAY_SIZE(_di_dsi_init_config0));
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DSI(_DSIREG(tegra_t210 ? DSI_INIT_SEQ_DATA_15 : DSI_INIT_SEQ_DATA_15_B01)) = 0;
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reg_write_array((u32 *)DSI_BASE, _di_dsi_init_config1, ARRAY_SIZE(_di_dsi_init_config1));
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// Reset pad trimmers for T210B01.
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if (!tegra_t210)
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exec_cfg((u32 *)DSI_BASE, _di_dsi_init_pads_t210b01, CFG_SIZE(_di_dsi_init_pads_t210b01));
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reg_write_array((u32 *)DSI_BASE, _di_dsi_init_pads_t210b01, ARRAY_SIZE(_di_dsi_init_pads_t210b01));
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// Setup init sequence packets and timings.
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exec_cfg((u32 *)DSI_BASE, _di_dsi_init_timing_pkt_config2, CFG_SIZE(_di_dsi_init_timing_pkt_config2));
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DSI(_DSIREG(DSI_PHY_TIMING_0)) = tegra_t210 ? 0x6070601 : 0x6070603; // DSI_THSPREPR: 1 : 3.
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exec_cfg((u32 *)DSI_BASE, _di_dsi_init_timing_pwrctrl_config, CFG_SIZE(_di_dsi_init_timing_pwrctrl_config));
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DSI(_DSIREG(DSI_PHY_TIMING_0)) = tegra_t210 ? 0x6070601 : 0x6070603; // DSI_THSPREPR: 1 : 3.
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exec_cfg((u32 *)DSI_BASE, _di_dsi_init_timing_pkt_config3, CFG_SIZE(_di_dsi_init_timing_pkt_config3));
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// Setup init sequence packets, timings and power on DSI.
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reg_write_array((u32 *)DSI_BASE, _di_dsi_init_config2, ARRAY_SIZE(_di_dsi_init_config2));
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usleep(10000);
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// Enable LCD Reset.
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@ -505,9 +484,9 @@ void display_init()
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{
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case PANEL_SAM_AMS699VC01:
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_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 180000);
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// Set color mode to natural. Stock is Saturated (0x00). (Reset value is 0x20).
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// Set color mode to basic (natural). Stock is Saturated (0x00). (Reset value is 0x20).
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_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE_PARAM,
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MIPI_DCS_PRIV_SM_SET_COLOR_MODE | (DCS_SM_COLOR_MODE_NATURAL << 8), 0);
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MIPI_DCS_PRIV_SM_SET_COLOR_MODE | (DCS_SM_COLOR_MODE_BASIC << 8), 0);
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// Enable backlight and smooth PWM.
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_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE_PARAM,
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MIPI_DCS_SET_CONTROL_DISPLAY | ((DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL | DCS_CONTROL_DISPLAY_DIMMING_CTRL) << 8), 0);
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@ -537,7 +516,7 @@ void display_init()
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break;
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case PANEL_JDI_XXX062M:
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exec_cfg((u32 *)DSI_BASE, _di_dsi_panel_init_config_jdi, CFG_SIZE(_di_dsi_panel_init_config_jdi));
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reg_write_array((u32 *)DSI_BASE, _di_dsi_panel_init_config_jdi, ARRAY_SIZE(_di_dsi_panel_init_config_jdi));
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_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 180000);
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break;
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@ -578,21 +557,24 @@ void display_init()
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clock_enable_plld(1, 24, false, tegra_t210);
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// Finalize DSI init packet sequence configuration.
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DSI(_DSIREG(DSI_PAD_CONTROL_1)) = 0;
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DSI(_DSIREG(DSI_PHY_TIMING_0)) = tegra_t210 ? 0x6070601 : 0x6070603;
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exec_cfg((u32 *)DSI_BASE, _di_dsi_init_seq_pkt_final_config, CFG_SIZE(_di_dsi_init_seq_pkt_final_config));
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reg_write_array((u32 *)DSI_BASE, _di_dsi_init_seq_pkt_final_config, ARRAY_SIZE(_di_dsi_init_seq_pkt_final_config));
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// Set 1-by-1 pixel/clock and pixel clock to 234 / 3 = 78 MHz. For 60 Hz refresh rate.
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DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4); // 4: div3.
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// Set DSI mode.
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exec_cfg((u32 *)DSI_BASE, _di_dsi_mode_config, CFG_SIZE(_di_dsi_mode_config));
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reg_write_array((u32 *)DSI_BASE, _di_dsi_mode_config, ARRAY_SIZE(_di_dsi_mode_config));
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usleep(10000);
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// Calibrate display communication pads.
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u32 loops = tegra_t210 ? 1 : 2; // Calibrate pads 2 times on T210B01.
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exec_cfg((u32 *)MIPI_CAL_BASE, _di_mipi_pad_cal_config, CFG_SIZE(_di_mipi_pad_cal_config));
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for (u32 i = 0; i < loops; i++)
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/*
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* Calibrate display communication pads.
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* When switching to the 16ff pad brick, the clock lane termination control
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* is separated from data lane termination. This change of the mipi cal
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* brings in a bug that the DSI pad clock termination code can't be loaded
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* in one time calibration. Trigger calibration twice.
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*/
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reg_write_array((u32 *)MIPI_CAL_BASE, _di_mipi_pad_cal_config, ARRAY_SIZE(_di_mipi_pad_cal_config));
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for (u32 i = 0; i < 2; i++)
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{
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// Set MIPI bias pad config.
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MIPI_CAL(_DSIREG(MIPI_CAL_MIPI_BIAS_PAD_CFG2)) = 0x10010;
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@ -601,22 +583,25 @@ void display_init()
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// Set pad trimmers and set MIPI DSI cal offsets.
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if (tegra_t210)
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{
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exec_cfg((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210, CFG_SIZE(_di_dsi_pad_cal_config_t210));
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exec_cfg((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_offsets_config_t210, CFG_SIZE(_di_mipi_dsi_cal_offsets_config_t210));
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reg_write_array((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210, ARRAY_SIZE(_di_dsi_pad_cal_config_t210));
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reg_write_array((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_prod_config_t210, ARRAY_SIZE(_di_mipi_dsi_cal_prod_config_t210));
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}
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else
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{
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exec_cfg((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210b01, CFG_SIZE(_di_dsi_pad_cal_config_t210b01));
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exec_cfg((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_offsets_config_t210b01, CFG_SIZE(_di_mipi_dsi_cal_offsets_config_t210b01));
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reg_write_array((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210b01, ARRAY_SIZE(_di_dsi_pad_cal_config_t210b01));
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reg_write_array((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_prod_config_t210b01, ARRAY_SIZE(_di_mipi_dsi_cal_prod_config_t210b01));
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}
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// Reset all MIPI cal offsets and start calibration.
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exec_cfg((u32 *)MIPI_CAL_BASE, _di_mipi_start_dsi_cal_config, CFG_SIZE(_di_mipi_start_dsi_cal_config));
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// Reset all unused MIPI cal offsets.
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reg_write_array((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_unused_config, ARRAY_SIZE(_di_mipi_dsi_cal_unused_config));
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// Set Prescale/filter and start calibration.
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MIPI_CAL(_DSIREG(MIPI_CAL_MIPI_CAL_CTRL)) = 0x2A000001;
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}
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usleep(10000);
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// Enable video display controller.
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exec_cfg((u32 *)DISPLAY_A_BASE, _di_dc_video_enable_config, CFG_SIZE(_di_dc_video_enable_config));
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reg_write_array((u32 *)DISPLAY_A_BASE, _di_dc_video_enable_config, ARRAY_SIZE(_di_dc_video_enable_config));
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}
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void display_backlight_pwm_init()
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@ -624,12 +609,15 @@ void display_backlight_pwm_init()
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if (_display_id == PANEL_SAM_AMS699VC01)
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return;
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// Enable PWM clock.
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clock_enable_pwm();
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// Enable PWM and set it to 25KHz PFM. 29.5KHz is stock.
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PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN;
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PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & ~PINMUX_FUNC_MASK) | 1; // Set PWM0 mode.
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usleep(2);
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gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight power mode.
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}
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@ -650,9 +638,9 @@ static void _display_dsi_backlight_brightness(u32 duty)
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u16 bl_ctrl = byte_swap_16((u16)candela);
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display_dsi_vblank_write(MIPI_DCS_SET_BRIGHTNESS, 2, &bl_ctrl);
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// Wait for backlight to completely turn off. 6+1 frames.
|
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// Wait for backlight to completely turn off. 6 frames.
|
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if (!duty)
|
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usleep(120000);
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usleep(100000);
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|
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_dsi_bl = duty;
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}
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@ -696,7 +684,10 @@ void display_backlight_brightness(u32 brightness, u32 step_delay)
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|
||||
u32 display_get_backlight_brightness()
|
||||
{
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return ((PWM(PWM_CONTROLLER_PWM_CSR_0) >> 16) & 0xFF);
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if (_display_id != PANEL_SAM_AMS699VC01)
|
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return ((PWM(PWM_CONTROLLER_PWM_CSR_0) >> 16) & 0xFF);
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else
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return _dsi_bl;
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}
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||||
|
||||
static void _display_panel_and_hw_end(bool no_panel_deinit)
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@ -713,14 +704,15 @@ static void _display_panel_and_hw_end(bool no_panel_deinit)
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DSI(_DSIREG(DSI_WR_DATA)) = (MIPI_DCS_SET_DISPLAY_OFF << 8) | MIPI_DSI_DCS_SHORT_WRITE;
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|
||||
// Wait for 5 frames (HOST1X_CH0_SYNC_SYNCPT_9).
|
||||
// Not here.
|
||||
// Not here. Wait for 1 frame manually.
|
||||
usleep(20000);
|
||||
|
||||
// Propagate changes to all register buffers and disable host cmd packets during video.
|
||||
DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = READ_MUX | WRITE_MUX;
|
||||
DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = READ_MUX_ACTIVE | WRITE_MUX_ACTIVE;
|
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0;
|
||||
|
||||
// De-initialize video controller.
|
||||
exec_cfg((u32 *)DISPLAY_A_BASE, _di_dc_video_disable_config, CFG_SIZE(_di_dc_video_disable_config));
|
||||
reg_write_array((u32 *)DISPLAY_A_BASE, _di_dc_video_disable_config, ARRAY_SIZE(_di_dc_video_disable_config));
|
||||
|
||||
// Set DISP1 clock source, parent clock and DSI/PCLK to low power mode.
|
||||
// T210: DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 100.0 MHz, PLLD_OUT0 (DSI-PCLK): 50.0 MHz. (PCLK: 16.66 MHz)
|
||||
@ -728,7 +720,7 @@ static void _display_panel_and_hw_end(bool no_panel_deinit)
|
||||
clock_enable_plld(3, 20, true, hw_get_chip_id() == GP_HIDREV_MAJOR_T210);
|
||||
|
||||
// Set timings for lowpower clocks.
|
||||
exec_cfg((u32 *)DSI_BASE, _di_dsi_timing_deinit_config, CFG_SIZE(_di_dsi_timing_deinit_config));
|
||||
reg_write_array((u32 *)DSI_BASE, _di_dsi_timing_deinit_config, ARRAY_SIZE(_di_dsi_timing_deinit_config));
|
||||
|
||||
if (_display_id != PANEL_SAM_AMS699VC01)
|
||||
usleep(10000);
|
||||
@ -737,11 +729,11 @@ static void _display_panel_and_hw_end(bool no_panel_deinit)
|
||||
switch (_display_id)
|
||||
{
|
||||
case PANEL_JDI_XXX062M:
|
||||
exec_cfg((u32 *)DSI_BASE, _di_dsi_panel_deinit_config_jdi, CFG_SIZE(_di_dsi_panel_deinit_config_jdi));
|
||||
reg_write_array((u32 *)DSI_BASE, _di_dsi_panel_deinit_config_jdi, ARRAY_SIZE(_di_dsi_panel_deinit_config_jdi));
|
||||
break;
|
||||
|
||||
case PANEL_AUO_A062TAN01:
|
||||
exec_cfg((u32 *)DSI_BASE, _di_dsi_panel_deinit_config_auo, CFG_SIZE(_di_dsi_panel_deinit_config_auo));
|
||||
reg_write_array((u32 *)DSI_BASE, _di_dsi_panel_deinit_config_auo, ARRAY_SIZE(_di_dsi_panel_deinit_config_auo));
|
||||
break;
|
||||
|
||||
case PANEL_INL_2J055IA_27A:
|
||||
@ -796,6 +788,10 @@ skip_panel_deinit:
|
||||
{
|
||||
gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_LOW); // LCD AVDD -5.4V disable.
|
||||
gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_LOW); // LCD AVDD +5.4V disable.
|
||||
|
||||
// Make sure LCD PWM backlight pin is in PWM0 mode.
|
||||
gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight PWM.
|
||||
PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = PINMUX_TRISTATE | PINMUX_PULL_DOWN | 1; // Set PWM0 mode.
|
||||
}
|
||||
usleep(10000);
|
||||
|
||||
@ -810,14 +806,7 @@ skip_panel_deinit:
|
||||
DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF);
|
||||
DSI(_DSIREG(DSI_POWER_CONTROL)) = 0;
|
||||
|
||||
// Switch LCD PWM backlight pin to special function mode and enable PWM0 mode.
|
||||
if (!_nx_aula)
|
||||
{
|
||||
gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight PWM.
|
||||
PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = PINMUX_TRISTATE | PINMUX_PULL_DOWN | 1; // Set PWM0 mode.
|
||||
}
|
||||
|
||||
// Disable LCD DVDD.
|
||||
// Disable DSI AVDD.
|
||||
max7762x_regulator_enable(REGULATOR_LDO0, false);
|
||||
}
|
||||
|
||||
@ -846,14 +835,15 @@ void display_set_decoded_panel_id(u32 id)
|
||||
|
||||
void display_color_screen(u32 color)
|
||||
{
|
||||
exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_one_color, CFG_SIZE(_di_win_one_color));
|
||||
// Disable all windows.
|
||||
reg_write_array((u32 *)DISPLAY_A_BASE, _di_win_one_color, ARRAY_SIZE(_di_win_one_color));
|
||||
|
||||
// Configure display to show single color.
|
||||
DISPLAY_A(_DIREG(DC_WIN_AD_WIN_OPTIONS)) = 0;
|
||||
DISPLAY_A(_DIREG(DC_WIN_BD_WIN_OPTIONS)) = 0;
|
||||
DISPLAY_A(_DIREG(DC_WIN_CD_WIN_OPTIONS)) = 0;
|
||||
DISPLAY_A(_DIREG(DC_DISP_BLEND_BACKGROUND_COLOR)) = color;
|
||||
DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = (DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE) | GENERAL_ACT_REQ;
|
||||
|
||||
// Arm and activate changes.
|
||||
DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE | WIN_D_UPDATE;
|
||||
DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ | WIN_D_ACT_REQ;
|
||||
usleep(35000); // Wait 2 frames. No need on Aula.
|
||||
|
||||
if (_display_id != PANEL_SAM_AMS699VC01)
|
||||
@ -862,58 +852,108 @@ void display_color_screen(u32 color)
|
||||
display_backlight_brightness(150, 0);
|
||||
}
|
||||
|
||||
u32 *display_init_framebuffer_pitch()
|
||||
u32 *display_init_window_a_pitch()
|
||||
{
|
||||
// Sanitize framebuffer area.
|
||||
memset((u32 *)IPL_FB_ADDRESS, 0, IPL_FB_SZ);
|
||||
|
||||
// This configures the framebuffer @ IPL_FB_ADDRESS with a resolution of 720x1280 (line stride 720).
|
||||
exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_framebuffer_pitch, CFG_SIZE(_di_win_framebuffer_pitch));
|
||||
reg_write_array((u32 *)DISPLAY_A_BASE, _di_winA_pitch, ARRAY_SIZE(_di_winA_pitch));
|
||||
//usleep(35000); // Wait 2 frames. No need on Aula.
|
||||
|
||||
return (u32 *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR));
|
||||
}
|
||||
|
||||
u32 *display_init_framebuffer_pitch_vic()
|
||||
u32 *display_init_window_a_pitch_vic()
|
||||
{
|
||||
// This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 720x1280 (line stride 720).
|
||||
if (_display_id != PANEL_SAM_AMS699VC01)
|
||||
usleep(8000); // Wait half frame for PWM to apply.
|
||||
exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_framebuffer_pitch_vic, CFG_SIZE(_di_win_framebuffer_pitch_vic));
|
||||
reg_write_array((u32 *)DISPLAY_A_BASE, _di_winA_pitch_vic, ARRAY_SIZE(_di_winA_pitch_vic));
|
||||
if (_display_id != PANEL_SAM_AMS699VC01)
|
||||
usleep(35000); // Wait 2 frames.
|
||||
|
||||
return (u32 *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR));
|
||||
}
|
||||
|
||||
u32 *display_init_framebuffer_pitch_inv()
|
||||
u32 *display_init_window_a_pitch_inv()
|
||||
{
|
||||
// This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 720x1280 (line stride 720).
|
||||
exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_framebuffer_pitch_inv, CFG_SIZE(_di_win_framebuffer_pitch_inv));
|
||||
reg_write_array((u32 *)DISPLAY_A_BASE, _di_winA_pitch_inv, ARRAY_SIZE(_di_winA_pitch_inv));
|
||||
usleep(35000); // Wait 2 frames. No need on Aula.
|
||||
|
||||
return (u32 *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR));
|
||||
}
|
||||
|
||||
u32 *display_init_framebuffer_block()
|
||||
u32 *display_init_window_a_block()
|
||||
{
|
||||
// This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 720x1280.
|
||||
exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_framebuffer_block, CFG_SIZE(_di_win_framebuffer_block));
|
||||
reg_write_array((u32 *)DISPLAY_A_BASE, _di_winA_block, ARRAY_SIZE(_di_winA_block));
|
||||
usleep(35000); // Wait 2 frames. No need on Aula.
|
||||
|
||||
return (u32 *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR));
|
||||
}
|
||||
|
||||
u32 *display_init_framebuffer_log()
|
||||
u32 *display_init_window_d_console()
|
||||
{
|
||||
// This configures the framebuffer @ LOG_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
|
||||
exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_framebuffer_log, CFG_SIZE(_di_win_framebuffer_log));
|
||||
reg_write_array((u32 *)DISPLAY_A_BASE, _di_winD_log, ARRAY_SIZE(_di_winD_log));
|
||||
|
||||
return (u32 *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR));
|
||||
}
|
||||
|
||||
void display_activate_console()
|
||||
void display_window_disable(u32 window)
|
||||
{
|
||||
// Select window C.
|
||||
DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = BIT(WINDOW_SELECT + window);
|
||||
|
||||
// Disable window C.
|
||||
DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = 0;
|
||||
|
||||
// Arm and activate changes.
|
||||
DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | BIT(WIN_UPDATE + window);
|
||||
DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | BIT(WIN_ACT_REQ + window);
|
||||
}
|
||||
|
||||
void display_set_framebuffer(u32 window, void *fb)
|
||||
{
|
||||
// Select window.
|
||||
DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = BIT(WINDOW_SELECT + window);
|
||||
|
||||
// Set new fb address.
|
||||
DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR)) = (u32)fb;
|
||||
|
||||
// Arm and activate changes.
|
||||
DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | BIT(WIN_UPDATE + window);
|
||||
DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | BIT(WIN_ACT_REQ + window);
|
||||
}
|
||||
|
||||
void display_move_framebuffer(u32 window, void *fb)
|
||||
{
|
||||
// Select window.
|
||||
DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = BIT(WINDOW_SELECT + window);
|
||||
|
||||
// Get current framebuffer address.
|
||||
void *fb_curr = (void *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR));
|
||||
u32 win_size = DISPLAY_A(_DIREG(DC_WIN_PRESCALED_SIZE));
|
||||
win_size = (win_size & 0x7FFF) * ((win_size >> 16) & 0x1FFF);
|
||||
|
||||
// Copy fb over.
|
||||
memcpy(fb, fb_curr, win_size);
|
||||
|
||||
// Set new fb address.
|
||||
DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR)) = (u32)fb;
|
||||
|
||||
// Arm and activate changes.
|
||||
DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | BIT(WIN_UPDATE + window);
|
||||
DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | BIT(WIN_ACT_REQ + window);
|
||||
}
|
||||
|
||||
void display_window_d_console_enable()
|
||||
{
|
||||
// Only update active registers on vsync.
|
||||
DISPLAY_A(_DIREG(DC_CMD_REG_ACT_CONTROL)) = DISPLAY_A(_DIREG(DC_CMD_REG_ACT_CONTROL)) & ~WIN_D_ACT_HCNTR_SEL;
|
||||
|
||||
// Select window D.
|
||||
DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT;
|
||||
|
||||
@ -942,12 +982,9 @@ void display_activate_console()
|
||||
// Arm and activate changes.
|
||||
DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
|
||||
DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
|
||||
|
||||
// Re-select window A.
|
||||
DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_A_SELECT;
|
||||
}
|
||||
|
||||
void display_deactivate_console()
|
||||
void display_window_d_console_disable()
|
||||
{
|
||||
// Select window D.
|
||||
DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT;
|
||||
@ -965,18 +1002,15 @@ void display_deactivate_console()
|
||||
}
|
||||
|
||||
// Disable window D.
|
||||
DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0;
|
||||
DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0;
|
||||
DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = 0;
|
||||
|
||||
// Arm and activate changes.
|
||||
DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
|
||||
DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
|
||||
|
||||
// Re-select window A.
|
||||
DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_A_SELECT;
|
||||
}
|
||||
|
||||
void display_init_cursor(void *crs_fb, u32 size)
|
||||
void display_cursor_init(void *crs_fb, u32 size)
|
||||
{
|
||||
// Setup cursor.
|
||||
DISPLAY_A(_DIREG(DC_DISP_CURSOR_START_ADDR)) = CURSOR_CLIPPING(CURSOR_CLIP_WIN_A) | size | ((u32)crs_fb >> 10);
|
||||
@ -992,7 +1026,7 @@ void display_init_cursor(void *crs_fb, u32 size)
|
||||
DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | CURSOR_ACT_REQ;
|
||||
}
|
||||
|
||||
void display_set_pos_cursor(u32 x, u32 y)
|
||||
void display_cursor_set_pos(u32 x, u32 y)
|
||||
{
|
||||
// Set cursor position.
|
||||
DISPLAY_A(_DIREG(DC_DISP_CURSOR_POSITION)) = x | (y << 16);
|
||||
@ -1002,7 +1036,7 @@ void display_set_pos_cursor(u32 x, u32 y)
|
||||
DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | CURSOR_ACT_REQ;
|
||||
}
|
||||
|
||||
void display_deinit_cursor()
|
||||
void display_cursor_deinit()
|
||||
{
|
||||
DISPLAY_A(_DIREG(DC_DISP_BLEND_CURSOR_CONTROL)) = 0;
|
||||
DISPLAY_A(_DIREG(DC_DISP_DISP_WIN_OPTIONS)) &= ~CURSOR_ENABLE;
|
||||
|
207
bdk/display/di.h
207
bdk/display/di.h
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018-2023 CTCaer
|
||||
* Copyright (c) 2018-2024 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
@ -24,6 +24,11 @@
|
||||
#define DSI_VIDEO_DISABLED 0
|
||||
#define DSI_VIDEO_ENABLED 1
|
||||
|
||||
#define WINDOW_A 0
|
||||
#define WINDOW_B 1
|
||||
#define WINDOW_C 2
|
||||
#define WINDOW_D 3
|
||||
|
||||
/*! Display registers. */
|
||||
#define _DIREG(reg) ((reg) * 4)
|
||||
|
||||
@ -43,8 +48,8 @@
|
||||
|
||||
// DC_CMD non-shadowed command/sync registers.
|
||||
#define DC_CMD_GENERAL_INCR_SYNCPT 0x00
|
||||
#define SYNCPT_GENERAL_INDX(x) (((x) & 0xff) << 0)
|
||||
#define SYNCPT_GENERAL_COND(x) (((x) & 0xff) << 8)
|
||||
#define SYNCPT_GENERAL_INDX(x) (((x) & 0xFF) << 0)
|
||||
#define SYNCPT_GENERAL_COND(x) (((x) & 0xFF) << 8)
|
||||
#define COND_REG_WR_SAFE 3
|
||||
|
||||
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x01
|
||||
@ -52,7 +57,7 @@
|
||||
#define SYNCPT_CNTRL_NO_STALL BIT(8)
|
||||
|
||||
#define DC_CMD_CONT_SYNCPT_VSYNC 0x28
|
||||
#define SYNCPT_VSYNC_INDX(x) (((x) & 0xff) << 0)
|
||||
#define SYNCPT_VSYNC_INDX(x) (((x) & 0xFF) << 0)
|
||||
#define SYNCPT_VSYNC_ENABLE BIT(8)
|
||||
|
||||
#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
|
||||
@ -77,19 +82,24 @@
|
||||
#define DC_CMD_INT_ENABLE 0x39
|
||||
#define DC_CMD_INT_FRAME_END_INT BIT(1)
|
||||
#define DC_CMD_INT_V_BLANK_INT BIT(2)
|
||||
#define DC_CMD_INT_POLARITY 0x3B
|
||||
|
||||
#define DC_CMD_STATE_ACCESS 0x40
|
||||
#define READ_MUX BIT(0)
|
||||
#define WRITE_MUX BIT(2)
|
||||
#define READ_MUX_ASSEMBLY 0x0
|
||||
#define WRITE_MUX_ASSEMBLY 0x0
|
||||
#define READ_MUX_ACTIVE BIT(0)
|
||||
#define WRITE_MUX_ACTIVE BIT(2)
|
||||
|
||||
#define DC_CMD_STATE_CONTROL 0x41
|
||||
#define GENERAL_ACT_REQ BIT(0)
|
||||
#define WIN_ACT_REQ 1
|
||||
#define WIN_A_ACT_REQ BIT(1)
|
||||
#define WIN_B_ACT_REQ BIT(2)
|
||||
#define WIN_C_ACT_REQ BIT(3)
|
||||
#define WIN_D_ACT_REQ BIT(4)
|
||||
#define CURSOR_ACT_REQ BIT(7)
|
||||
#define GENERAL_UPDATE BIT(8)
|
||||
#define WIN_UPDATE 9
|
||||
#define WIN_A_UPDATE BIT(9)
|
||||
#define WIN_B_UPDATE BIT(10)
|
||||
#define WIN_C_UPDATE BIT(11)
|
||||
@ -98,6 +108,7 @@
|
||||
#define NC_HOST_TRIG BIT(24)
|
||||
|
||||
#define DC_CMD_DISPLAY_WINDOW_HEADER 0x42
|
||||
#define WINDOW_SELECT 4
|
||||
#define WINDOW_A_SELECT BIT(4)
|
||||
#define WINDOW_B_SELECT BIT(5)
|
||||
#define WINDOW_C_SELECT BIT(6)
|
||||
@ -137,6 +148,31 @@
|
||||
#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
|
||||
#define LSC0_OUTPUT_POLARITY_LOW BIT(24)
|
||||
|
||||
// CMU registers.
|
||||
#define DC_COM_CMU_CSC_KRR 0x32A
|
||||
#define DC_COM_CMU_CSC_KGR 0x32B
|
||||
#define DC_COM_CMU_CSC_KBR 0x32C
|
||||
#define DC_COM_CMU_CSC_KRG 0x32D
|
||||
#define DC_COM_CMU_CSC_KGG 0x32E
|
||||
#define DC_COM_CMU_CSC_KBG 0x32F
|
||||
#define DC_COM_CMU_CSC_KRB 0x330
|
||||
#define DC_COM_CMU_CSC_KGB 0x331
|
||||
#define DC_COM_CMU_CSC_KBB 0x332
|
||||
#define DC_COM_CMU_LUT1 0x336
|
||||
#define LUT1_ADDR(x) ((x) & 0xFF)
|
||||
#define LUT1_DATA(x) (((x) & 0xFFF) << 16)
|
||||
#define LUT1_READ_DATA(x) (((x) >> 16) & 0xFFF)
|
||||
#define DC_COM_CMU_LUT2 0x337
|
||||
#define LUT2_ADDR(x) ((x) & 0x3FF)
|
||||
#define LUT2_DATA(x) (((x) & 0xFF) << 16)
|
||||
#define LUT2_READ_DATA(x) (((x) >> 16) & 0xFF)
|
||||
#define DC_COM_CMU_LUT1_READ 0x338
|
||||
#define LUT1_READ_ADDR(x) (((x) & 0xFF) << 8)
|
||||
#define LUT1_READ_EN BIT(0)
|
||||
#define DC_COM_CMU_LUT2_READ 0x339
|
||||
#define LUT2_READ_ADDR(x) (((x) & 0x3FF) << 8)
|
||||
#define LUT2_READ_EN BIT(0)
|
||||
|
||||
#define DC_COM_DSC_TOP_CTL 0x33E
|
||||
|
||||
// DC_DISP shadowed registers.
|
||||
@ -153,30 +189,30 @@
|
||||
#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
|
||||
|
||||
#define DC_DISP_DISP_TIMING_OPTIONS 0x405
|
||||
#define VSYNC_H_POSITION(x) (((x) & 0x1fff) << 0)
|
||||
#define VSYNC_H_POSITION(x) (((x) & 0x1FFF) << 0)
|
||||
|
||||
#define DC_DISP_REF_TO_SYNC 0x406
|
||||
#define H_REF_TO_SYNC(x) (((x) & 0x1fff) << 0) // Min 0 pixel clock.
|
||||
#define V_REF_TO_SYNC(x) (((x) & 0x1fff) << 16) // Min 1 line clock.
|
||||
#define H_REF_TO_SYNC(x) (((x) & 0x1FFF) << 0) // Min 0 pixel clock.
|
||||
#define V_REF_TO_SYNC(x) (((x) & 0x1FFF) << 16) // Min 1 line clock.
|
||||
|
||||
#define DC_DISP_SYNC_WIDTH 0x407
|
||||
#define H_SYNC_WIDTH(x) (((x) & 0x1fff) << 0) // Min 1 pixel clock.
|
||||
#define V_SYNC_WIDTH(x) (((x) & 0x1fff) << 16) // Min 1 line clock.
|
||||
#define H_SYNC_WIDTH(x) (((x) & 0x1FFF) << 0) // Min 1 pixel clock.
|
||||
#define V_SYNC_WIDTH(x) (((x) & 0x1FFF) << 16) // Min 1 line clock.
|
||||
|
||||
#define DC_DISP_BACK_PORCH 0x408
|
||||
#define H_BACK_PORCH(x) (((x) & 0x1fff) << 0)
|
||||
#define V_BACK_PORCH(x) (((x) & 0x1fff) << 16)
|
||||
#define H_BACK_PORCH(x) (((x) & 0x1FFF) << 0)
|
||||
#define V_BACK_PORCH(x) (((x) & 0x1FFF) << 16)
|
||||
|
||||
#define DC_DISP_ACTIVE 0x409
|
||||
#define H_DISP_ACTIVE(x) (((x) & 0x1fff) << 0) // Min 16 pixel clock.
|
||||
#define V_DISP_ACTIVE(x) (((x) & 0x1fff) << 16) // Min 16 line clock.
|
||||
#define H_DISP_ACTIVE(x) (((x) & 0x1FFF) << 0) // Min 16 pixel clock.
|
||||
#define V_DISP_ACTIVE(x) (((x) & 0x1FFF) << 16) // Min 16 line clock.
|
||||
|
||||
#define DC_DISP_FRONT_PORCH 0x40A
|
||||
#define H_FRONT_PORCH(x) (((x) & 0x1fff) << 0) // Min -=PS_=-H_REF_TO_SYNC + 1
|
||||
#define V_FRONT_PORCH(x) (((x) & 0x1fff) << 16) // Min -=PS_=-V_REF_TO_SYNC + 1
|
||||
#define H_FRONT_PORCH(x) (((x) & 0x1FFF) << 0) // Min -=PS_=-H_REF_TO_SYNC + 1
|
||||
#define V_FRONT_PORCH(x) (((x) & 0x1FFF) << 16) // Min -=PS_=-V_REF_TO_SYNC + 1
|
||||
|
||||
#define DC_DISP_DISP_CLOCK_CONTROL 0x42E
|
||||
#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
|
||||
#define SHIFT_CLK_DIVIDER(x) ((x) & 0xFF)
|
||||
#define PIXEL_CLK_DIVIDER_PCD1 (0 << 8)
|
||||
#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
|
||||
#define PIXEL_CLK_DIVIDER_PCD2 (2 << 8)
|
||||
@ -207,11 +243,7 @@
|
||||
#define DISP_ORDER_BLUE_RED (1 << 9)
|
||||
|
||||
#define DC_DISP_DISP_COLOR_CONTROL 0x430
|
||||
#define DITHER_CONTROL_MASK (3 << 8)
|
||||
#define DITHER_CONTROL_DISABLE (0 << 8)
|
||||
#define DITHER_CONTROL_ORDERED (2 << 8)
|
||||
#define DITHER_CONTROL_ERRDIFF (3 << 8)
|
||||
#define BASE_COLOR_SIZE_MASK (0xf << 0)
|
||||
#define BASE_COLOR_SIZE_MASK (0xF << 0)
|
||||
#define BASE_COLOR_SIZE_666 (0 << 0)
|
||||
#define BASE_COLOR_SIZE_111 (1 << 0)
|
||||
#define BASE_COLOR_SIZE_222 (2 << 0)
|
||||
@ -221,6 +253,13 @@
|
||||
#define BASE_COLOR_SIZE_565 (6 << 0)
|
||||
#define BASE_COLOR_SIZE_332 (7 << 0)
|
||||
#define BASE_COLOR_SIZE_888 (8 << 0)
|
||||
#define DITHER_CONTROL_MASK (3 << 8)
|
||||
#define DITHER_CONTROL_DISABLE (0 << 8)
|
||||
#define DITHER_CONTROL_ORDERED (2 << 8)
|
||||
#define DITHER_CONTROL_ERRDIFF (3 << 8)
|
||||
#define DISP_COLOR_SWAP BIT(16)
|
||||
#define BLANK_COLOR_WHITE BIT(17)
|
||||
#define CMU_ENABLE BIT(20)
|
||||
|
||||
#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
|
||||
#define SC0_H_QUALIFIER_NONE BIT(0)
|
||||
@ -242,6 +281,7 @@
|
||||
#define CURSOR_COLOR(r,g,b) (((r) & 0xFF) | (((g) & 0xFF) << 8) | (((b) & 0xFF) << 16))
|
||||
|
||||
#define DC_DISP_CURSOR_START_ADDR 0x43E
|
||||
#define DC_DISP_CURSOR_START_ADDR_NS 0x43F
|
||||
#define CURSOR_CLIPPING(w) ((w) << 28)
|
||||
#define CURSOR_CLIP_WIN_A 1
|
||||
#define CURSOR_CLIP_WIN_B 2
|
||||
@ -253,6 +293,7 @@
|
||||
#define DC_DISP_CURSOR_POSITION 0x440
|
||||
#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4
|
||||
#define DC_DISP_CURSOR_START_ADDR_HI 0x4EC
|
||||
#define DC_DISP_CURSOR_START_ADDR_HI_NS 0x4ED
|
||||
#define DC_DISP_BLEND_CURSOR_CONTROL 0x4F1
|
||||
#define CURSOR_BLEND_2BIT (0 << 24)
|
||||
#define CURSOR_BLEND_R8G8B8A8 (1 << 24)
|
||||
@ -269,17 +310,22 @@
|
||||
#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4
|
||||
|
||||
#define DC_WINC_COLOR_PALETTE 0x500
|
||||
#define DC_WINC_COLOR_PALETTE_IDX(off) (DC_WINC_COLOR_PALETTE + (off))
|
||||
#define COLOR_PALETTE_IDX(off) (DC_WINC_COLOR_PALETTE + (off))
|
||||
#define COLOR_PALETTE_RGB(rgb) (byte_swap_32(rgb) >> 8)
|
||||
#define DC_WINC_PALETTE_COLOR_EXT 0x600
|
||||
|
||||
#define DC_WIN_CSC_YOF 0x611
|
||||
#define DC_WIN_CSC_KYRGB 0x612
|
||||
#define DC_WIN_CSC_KUR 0x613
|
||||
#define DC_WIN_CSC_KVR 0x614
|
||||
#define DC_WIN_CSC_KUG 0x615
|
||||
#define DC_WIN_CSC_KVG 0x616
|
||||
#define DC_WIN_CSC_KUB 0x617
|
||||
#define DC_WIN_CSC_KVB 0x618
|
||||
#define DC_WINC_H_FILTER_P(p) (0x601 + (p))
|
||||
#define DC_WINC_V_FILTER_P(p) (0x619 + (p))
|
||||
#define DC_WINC_H_FILTER_HI_P(p) (0x629 + (p))
|
||||
|
||||
#define DC_WINC_CSC_YOF 0x611
|
||||
#define DC_WINC_CSC_KYRGB 0x612
|
||||
#define DC_WINC_CSC_KUR 0x613
|
||||
#define DC_WINC_CSC_KVR 0x614
|
||||
#define DC_WINC_CSC_KUG 0x615
|
||||
#define DC_WINC_CSC_KVG 0x616
|
||||
#define DC_WINC_CSC_KUB 0x617
|
||||
#define DC_WINC_CSC_KVB 0x618
|
||||
#define DC_WIN_AD_WIN_OPTIONS 0xB80
|
||||
#define DC_WIN_BD_WIN_OPTIONS 0xD80
|
||||
#define DC_WIN_CD_WIN_OPTIONS 0xF80
|
||||
@ -290,15 +336,17 @@
|
||||
#define V_DIRECTION BIT(2)
|
||||
#define SCAN_COLUMN BIT(4)
|
||||
#define COLOR_EXPAND BIT(6)
|
||||
#define H_FILTER_ENABLE BIT(8)
|
||||
#define V_FILTER_ENABLE BIT(10)
|
||||
#define COLOR_PALETTE_ENABLE BIT(16)
|
||||
#define CSC_ENABLE BIT(18)
|
||||
#define DV_ENABLE BIT(20)
|
||||
#define WIN_ENABLE BIT(30)
|
||||
#define H_FILTER_EXPAND BIT(31)
|
||||
|
||||
#define DC_WIN_BUFFER_CONTROL 0x702
|
||||
#define BUFFER_CONTROL_HOST 0
|
||||
#define BUFFER_CONTROL_VI 1
|
||||
#define BUFFER_CONTROL_EPP 2
|
||||
#define BUFFER_CONTROL_MPEGE 3
|
||||
#define BUFFER_CONTROL_SB2D 4
|
||||
|
||||
#define DC_WIN_COLOR_DEPTH 0x703
|
||||
@ -324,6 +372,10 @@
|
||||
#define WIN_COLOR_DEPTH_YUV422R 0x17
|
||||
#define WIN_COLOR_DEPTH_YCbCr422RA 0x18
|
||||
#define WIN_COLOR_DEPTH_YUV422RA 0x19
|
||||
#define WIN_COLOR_DEPTH_X1R5G5B5 0x1E
|
||||
#define WIN_COLOR_DEPTH_R5G5B5X1 0x1F
|
||||
#define WIN_COLOR_DEPTH_X1B5G5R5 0x20
|
||||
#define WIN_COLOR_DEPTH_B5G5R5X1 0x21
|
||||
#define WIN_COLOR_DEPTH_YCbCr444P 0x29
|
||||
#define WIN_COLOR_DEPTH_YCrCb420SP 0x2A
|
||||
#define WIN_COLOR_DEPTH_YCbCr420SP 0x2B
|
||||
@ -338,33 +390,37 @@
|
||||
#define WIN_COLOR_DEPTH_YUV444SP 0x3C
|
||||
|
||||
#define DC_WIN_POSITION 0x704
|
||||
#define H_POSITION(x) (((x) & 0xffff) << 0) // Support negative.
|
||||
#define V_POSITION(x) (((x) & 0xffff) << 16) // Support negative.
|
||||
#define H_POSITION(x) (((x) & 0xFFFF) << 0) // Support negative.
|
||||
#define V_POSITION(x) (((x) & 0xFFFF) << 16) // Support negative.
|
||||
|
||||
#define DC_WIN_SIZE 0x705
|
||||
#define H_SIZE(x) (((x) & 0x1fff) << 0)
|
||||
#define V_SIZE(x) (((x) & 0x1fff) << 16)
|
||||
#define H_SIZE(x) (((x) & 0x1FFF) << 0)
|
||||
#define V_SIZE(x) (((x) & 0x1FFF) << 16)
|
||||
|
||||
#define DC_WIN_PRESCALED_SIZE 0x706
|
||||
#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0)
|
||||
#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16)
|
||||
#define H_PRESCALED_SIZE(x) (((x) & 0x7FFF) << 0)
|
||||
#define V_PRESCALED_SIZE(x) (((x) & 0x1FFF) << 16)
|
||||
|
||||
#define DC_WIN_H_INITIAL_DDA 0x707
|
||||
#define DC_WIN_V_INITIAL_DDA 0x708
|
||||
|
||||
#define DC_WIN_DDA_INC 0x709
|
||||
#define H_DDA_INC(x) (((x) & 0xffff) << 0)
|
||||
#define V_DDA_INC(x) (((x) & 0xffff) << 16)
|
||||
#define H_DDA_INC(x) (((x) & 0xFFFF) << 0)
|
||||
#define V_DDA_INC(x) (((x) & 0xFFFF) << 16)
|
||||
|
||||
#define DC_WIN_LINE_STRIDE 0x70A
|
||||
#define LINE_STRIDE(x) (x)
|
||||
#define UV_LINE_STRIDE(x) (((x) & 0xffff) << 16)
|
||||
#define UV_LINE_STRIDE(x) (((x) & 0xFFFF) << 16)
|
||||
|
||||
#define DC_WIN_DV_CONTROL 0x70E
|
||||
#define DV_CTRL_R(r) (((r) & 7) << 16)
|
||||
#define DV_CTRL_G(g) (((g) & 7) << 8)
|
||||
#define DV_CTRL_B(b) (((b) & 7) << 0)
|
||||
|
||||
#define DC_WINBUF_BLEND_LAYER_CONTROL 0x716
|
||||
#define WIN_BLEND_DEPTH(x) (((x) & 0xff) << 0)
|
||||
#define WIN_K1(x) (((x) & 0xff) << 8)
|
||||
#define WIN_K2(x) (((x) & 0xff) << 16)
|
||||
#define WIN_BLEND_DEPTH(x) (((x) & 0xFF) << 0)
|
||||
#define WIN_K1(x) (((x) & 0xFF) << 8)
|
||||
#define WIN_K2(x) (((x) & 0xFF) << 16)
|
||||
#define WIN_BLEND_ENABLE (0 << 24)
|
||||
#define WIN_BLEND_BYPASS (1 << 24)
|
||||
|
||||
@ -395,8 +451,8 @@
|
||||
#define WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_K2 (3 << 12)
|
||||
|
||||
#define DC_WINBUF_BLEND_ALPHA_1BIT 0x719
|
||||
#define WIN_ALPHA_1BIT_WEIGHT0(x) (((x) & 0xff) << 0)
|
||||
#define WIN_ALPHA_1BIT_WEIGHT1(x) (((x) & 0xff) << 8)
|
||||
#define WIN_ALPHA_1BIT_WEIGHT0(x) (((x) & 0xFF) << 0)
|
||||
#define WIN_ALPHA_1BIT_WEIGHT1(x) (((x) & 0xFF) << 8)
|
||||
|
||||
/*! The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER). */
|
||||
#define DC_WINBUF_START_ADDR 0x800
|
||||
@ -408,6 +464,8 @@
|
||||
#define BLOCK (2 << 0)
|
||||
#define BLOCK_HEIGHT(x) (((x) & 0x7) << 4)
|
||||
|
||||
#define DC_WINBUF_MEMFETCH_CONTROL 0x82B
|
||||
|
||||
/*! Display serial interface registers. */
|
||||
#define _DSIREG(reg) ((reg) * 4)
|
||||
|
||||
@ -486,8 +544,8 @@
|
||||
#define DSI_PKT_LEN_2_3 0x35
|
||||
#define DSI_PKT_LEN_4_5 0x36
|
||||
#define DSI_PKT_LEN_6_7 0x37
|
||||
#define PKT0_LEN(x) (((x) & 0xffff) << 0)
|
||||
#define PKT1_LEN(x) (((x) & 0xffff) << 16)
|
||||
#define PKT0_LEN(x) (((x) & 0xFFFF) << 0)
|
||||
#define PKT1_LEN(x) (((x) & 0xFFFF) << 16)
|
||||
|
||||
#define DSI_PHY_TIMING_0 0x3C
|
||||
#define DSI_PHY_TIMING_1 0x3D
|
||||
@ -495,20 +553,20 @@
|
||||
#define DSI_BTA_TIMING 0x3F
|
||||
|
||||
#define DSI_TIMEOUT_0 0x44
|
||||
#define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0)
|
||||
#define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16)
|
||||
#define DSI_TIMEOUT_HTX(x) (((x) & 0xFFFF) << 0)
|
||||
#define DSI_TIMEOUT_LRX(x) (((x) & 0xFFFF) << 16)
|
||||
|
||||
#define DSI_TIMEOUT_1 0x45
|
||||
#define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0)
|
||||
#define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16)
|
||||
#define DSI_TIMEOUT_TA(x) (((x) & 0xFFFF) << 0)
|
||||
#define DSI_TIMEOUT_PR(x) (((x) & 0xFFFF) << 16)
|
||||
|
||||
#define DSI_TO_TALLY 0x46
|
||||
|
||||
#define DSI_PAD_CONTROL_0 0x4B
|
||||
#define DSI_PAD_CONTROL_VS1_PDIO_CLK BIT(8)
|
||||
#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0)
|
||||
#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xF) << 0)
|
||||
#define DSI_PAD_CONTROL_VS1_PULLDN_CLK BIT(24)
|
||||
#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16)
|
||||
#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xF) << 16)
|
||||
|
||||
#define DSI_PAD_CONTROL_CD 0x4C
|
||||
#define DSI_VIDEO_MODE_CONTROL 0x4E
|
||||
@ -810,6 +868,12 @@ void display_wait_interrupt(u32 intr);
|
||||
u16 display_get_decoded_panel_id();
|
||||
void display_set_decoded_panel_id(u32 id);
|
||||
|
||||
/*! MIPI DCS register management */
|
||||
int display_dsi_read(u8 cmd, u32 len, void *data);
|
||||
int display_dsi_vblank_read(u8 cmd, u32 len, void *data);
|
||||
void display_dsi_write(u8 cmd, u32 len, void *data);
|
||||
void display_dsi_vblank_write(u8 cmd, u32 len, void *data);
|
||||
|
||||
/*! Show one single color on the display. */
|
||||
void display_color_screen(u32 color);
|
||||
|
||||
@ -818,21 +882,22 @@ void display_backlight(bool enable);
|
||||
void display_backlight_brightness(u32 brightness, u32 step_delay);
|
||||
u32 display_get_backlight_brightness();
|
||||
|
||||
/*! Init display in full 720x1280 resolution (B8G8R8A8, line stride 720, framebuffer size = 720*1280*4 bytes). */
|
||||
u32 *display_init_framebuffer_pitch();
|
||||
u32 *display_init_framebuffer_pitch_vic();
|
||||
u32 *display_init_framebuffer_pitch_inv();
|
||||
u32 *display_init_framebuffer_block();
|
||||
u32 *display_init_framebuffer_log();
|
||||
void display_activate_console();
|
||||
void display_deactivate_console();
|
||||
void display_init_cursor(void *crs_fb, u32 size);
|
||||
void display_set_pos_cursor(u32 x, u32 y);
|
||||
void display_deinit_cursor();
|
||||
u32 *display_init_window_a_pitch();
|
||||
u32 *display_init_window_a_pitch_vic();
|
||||
u32 *display_init_window_a_pitch_inv();
|
||||
u32 *display_init_window_a_block();
|
||||
u32 *display_init_window_d_console();
|
||||
|
||||
int display_dsi_read(u8 cmd, u32 len, void *data);
|
||||
int display_dsi_vblank_read(u8 cmd, u32 len, void *data);
|
||||
void display_dsi_write(u8 cmd, u32 len, void *data);
|
||||
void display_dsi_vblank_write(u8 cmd, u32 len, void *data);
|
||||
void display_window_disable(u32 window);
|
||||
|
||||
void display_set_framebuffer(u32 window, void *fb);
|
||||
void display_move_framebuffer(u32 window, void *fb);
|
||||
|
||||
void display_window_d_console_enable();
|
||||
void display_window_d_console_disable();
|
||||
|
||||
void display_cursor_init(void *crs_fb, u32 size);
|
||||
void display_cursor_set_pos(u32 x, u32 y);
|
||||
void display_cursor_deinit();
|
||||
|
||||
#endif
|
||||
|
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018-2022 CTCaer
|
||||
* Copyright (c) 2018-2024 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
@ -16,37 +16,35 @@
|
||||
*/
|
||||
|
||||
// Display A config.
|
||||
static const cfg_op_t _di_dc_setup_win_config[] = {
|
||||
{DC_CMD_STATE_ACCESS, 0},
|
||||
static const reg_cfg_t _di_dc_setup_win_config[] = {
|
||||
{DC_CMD_STATE_ACCESS, READ_MUX_ASSEMBLY | WRITE_MUX_ASSEMBLY},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||
{DC_CMD_REG_ACT_CONTROL, WIN_A_ACT_HCNTR_SEL | WIN_B_ACT_HCNTR_SEL | WIN_C_ACT_HCNTR_SEL},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT | WINDOW_B_SELECT | WINDOW_C_SELECT},
|
||||
{DC_DISP_DC_MCCIF_FIFOCTRL, 0},
|
||||
{DC_DISP_DISP_MEM_HIGH_PRIORITY, 0},
|
||||
{DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0},
|
||||
{DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE},
|
||||
{DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL},
|
||||
{DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | SYNCPT_VSYNC_INDX(9)},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
|
||||
{DC_CMD_STATE_ACCESS, 0},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE | WIN_D_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ | WIN_D_ACT_REQ},
|
||||
|
||||
/* Setup Windows A/B/C */
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT | WINDOW_B_SELECT | WINDOW_C_SELECT},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT | WINDOW_B_SELECT | WINDOW_C_SELECT | WINDOW_D_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_WIN_DV_CONTROL, 0},
|
||||
/* Setup default YUV colorspace conversion coefficients */
|
||||
{DC_WIN_CSC_YOF, 0xF0},
|
||||
{DC_WIN_CSC_KYRGB, 0x12A},
|
||||
{DC_WIN_CSC_KUR, 0},
|
||||
{DC_WIN_CSC_KVR, 0x198},
|
||||
{DC_WIN_CSC_KUG, 0x39B},
|
||||
{DC_WIN_CSC_KVG, 0x32F},
|
||||
{DC_WIN_CSC_KUB, 0x204},
|
||||
{DC_WIN_CSC_KVB, 0},
|
||||
{DC_WINC_CSC_YOF, 0xF0},
|
||||
{DC_WINC_CSC_KYRGB, 0x12A},
|
||||
{DC_WINC_CSC_KUR, 0},
|
||||
{DC_WINC_CSC_KVR, 0x198},
|
||||
{DC_WINC_CSC_KUG, 0x39B},
|
||||
{DC_WINC_CSC_KVG, 0x32F},
|
||||
{DC_WINC_CSC_KUB, 0x204},
|
||||
{DC_WINC_CSC_KVB, 0},
|
||||
/* End of color coefficients */
|
||||
|
||||
{DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
|
||||
@ -55,21 +53,18 @@ static const cfg_op_t _di_dc_setup_win_config[] = {
|
||||
{DC_COM_PIN_OUTPUT_POLARITY(3), 0},
|
||||
{DC_DISP_BLEND_BACKGROUND_COLOR, 0},
|
||||
{DC_COM_CRC_CONTROL, 0},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT | WINDOW_B_SELECT | WINDOW_C_SELECT},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE | WIN_D_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ | WIN_D_ACT_REQ},
|
||||
{DC_WINBUF_BLEND_LAYER_CONTROL, WIN_BLEND_BYPASS | WIN_BLEND_DEPTH(255)},
|
||||
{DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT | WINDOW_B_SELECT | WINDOW_C_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_DISP_DISP_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_STOP},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE | WIN_D_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ | WIN_D_ACT_REQ}
|
||||
};
|
||||
|
||||
// DSI Init config.
|
||||
static const cfg_op_t _di_dsi_init_irq_pkt_config0[] = {
|
||||
static const reg_cfg_t _di_dsi_init_config0[] = {
|
||||
{DSI_WR_DATA, 0},
|
||||
{DSI_INT_ENABLE, 0},
|
||||
{DSI_INT_STATUS, 0},
|
||||
@ -79,7 +74,7 @@ static const cfg_op_t _di_dsi_init_irq_pkt_config0[] = {
|
||||
{DSI_INIT_SEQ_DATA_2, 0},
|
||||
{DSI_INIT_SEQ_DATA_3, 0}
|
||||
};
|
||||
static const cfg_op_t _di_dsi_init_irq_pkt_config1[] = {
|
||||
static const reg_cfg_t _di_dsi_init_config1[] = {
|
||||
{DSI_DCS_CMDS, 0},
|
||||
{DSI_PKT_SEQ_0_LO, 0},
|
||||
{DSI_PKT_SEQ_1_LO, 0},
|
||||
@ -95,7 +90,7 @@ static const cfg_op_t _di_dsi_init_irq_pkt_config1[] = {
|
||||
{DSI_PKT_SEQ_5_HI, 0},
|
||||
{DSI_CONTROL, 0}
|
||||
};
|
||||
static const cfg_op_t _di_dsi_init_pads_t210b01[] = {
|
||||
static const reg_cfg_t _di_dsi_init_pads_t210b01[] = {
|
||||
{DSI_PAD_CONTROL_1, 0},
|
||||
{DSI_PAD_CONTROL_2, 0},
|
||||
{DSI_PAD_CONTROL_3, 0},
|
||||
@ -104,7 +99,7 @@ static const cfg_op_t _di_dsi_init_pads_t210b01[] = {
|
||||
{DSI_PAD_CONTROL_6_B01, 0},
|
||||
{DSI_PAD_CONTROL_7_B01, 0}
|
||||
};
|
||||
static const cfg_op_t _di_dsi_init_timing_pkt_config2[] = {
|
||||
static const reg_cfg_t _di_dsi_init_config2[] = {
|
||||
{DSI_PAD_CONTROL_CD, 0},
|
||||
{DSI_SOL_DELAY, 24},
|
||||
{DSI_MAX_THRESHOLD, 480},
|
||||
@ -114,23 +109,21 @@ static const cfg_op_t _di_dsi_init_timing_pkt_config2[] = {
|
||||
{DSI_PKT_LEN_2_3, 0},
|
||||
{DSI_PKT_LEN_4_5, 0},
|
||||
{DSI_PKT_LEN_6_7, 0},
|
||||
{DSI_PAD_CONTROL_1, 0}
|
||||
};
|
||||