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bdk: minerva: l4t: adjust sdmmc1 la and freq table

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- LA is tightened up
- Copied frequencies are now 204/408/800/1333/1600/OC (from 204/666/800/1600/OC)
This commit is contained in:
CTCaer 2024-03-27 09:25:29 +02:00
parent 42c02e97e8
commit e846f4576e
2 changed files with 27 additions and 26 deletions
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50
bdk/mem/minerva.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019-2022 CTCaer * Copyright (c) 2019-2024 CTCaer
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@ -155,13 +155,13 @@ void minerva_sdmmc_la_program(void *table, bool t210b01)
switch (freq) switch (freq)
{ {
case 204000: case 204000:
la_scale_regs[LA_SDMMC1_INDEX] = (la_scale_regs[LA_SDMMC1_INDEX] & 0xFF0000) | 75; la_scale_regs[LA_SDMMC1_INDEX] = (la_scale_regs[LA_SDMMC1_INDEX] & 0xFF0000) | 50;
break; break;
case 408000: case 408000:
la_scale_regs[LA_SDMMC1_INDEX] = (la_scale_regs[LA_SDMMC1_INDEX] & 0xFF0000) | 37; la_scale_regs[LA_SDMMC1_INDEX] = (la_scale_regs[LA_SDMMC1_INDEX] & 0xFF0000) | 25;
break; break;
default: default:
la_scale_regs[LA_SDMMC1_INDEX] = (la_scale_regs[LA_SDMMC1_INDEX] & 0xFF0000) | 30; la_scale_regs[LA_SDMMC1_INDEX] = (la_scale_regs[LA_SDMMC1_INDEX] & 0xFF0000) | 20;
break; break;
} }
} }
@ -206,6 +206,23 @@ void minerva_prep_boot_l4t(u32 oc_freq, u32 opt_custom)
mtc_cfg->table_entries++; mtc_cfg->table_entries++;
} }
// Trim table.
int entries = 0;
for (u32 i = 0; i < mtc_cfg->table_entries; i++)
{
// Copy frequencies from 204/408/800 MHz and 1333+ MHz.
int rate = mtc_cfg->mtc_table[i].rate_khz;
if (rate == FREQ_204 ||
rate == FREQ_408 ||
rate == FREQ_800 ||
rate >= FREQ_1333)
{
memcpy(&mtc_cfg->mtc_table[entries], &mtc_cfg->mtc_table[i], sizeof(emc_table_t));
entries++;
}
}
mtc_cfg->table_entries = entries;
// Set init frequency. // Set init frequency.
minerva_change_freq(FREQ_204); minerva_change_freq(FREQ_204);
@ -213,38 +230,21 @@ void minerva_prep_boot_l4t(u32 oc_freq, u32 opt_custom)
mtc_cfg->train_mode = OP_TRAIN; mtc_cfg->train_mode = OP_TRAIN;
for (u32 i = 0; i < mtc_cfg->table_entries; i++) for (u32 i = 0; i < mtc_cfg->table_entries; i++)
{ {
mtc_cfg->rate_to = mtc_cfg->mtc_table[i].rate_khz; // Skip already trained frequencies and OC freq (Arachne handles it).
// Skip already trained frequencies. if (mtc_cfg->mtc_table[i].trained || mtc_cfg->rate_to == oc_freq)
if (mtc_cfg->rate_to == FREQ_204 ||
mtc_cfg->rate_to == FREQ_800 ||
mtc_cfg->rate_to == FREQ_1600 ||
mtc_cfg->rate_to == oc_freq) // Skip OC freq since Arachne handles it.
continue; continue;
// Train frequency. // Train frequency.
mtc_cfg->rate_to = mtc_cfg->mtc_table[i].rate_khz;
minerva_cfg(mtc_cfg, NULL); minerva_cfg(mtc_cfg, NULL);
} }
// Do FSP WAR and scale to 800 MHz as boot freq. // Do FSP WAR and scale to 800 MHz as boot freq.
bool fsp_opwr_disabled = !(EMC(EMC_MRW3) & 0xC0); bool fsp_opwr_disabled = !(EMC(EMC_MRW3) & 0xC0);
if (fsp_opwr_disabled) if (fsp_opwr_disabled)
minerva_change_freq(FREQ_666); minerva_change_freq(FREQ_1333);
minerva_change_freq(FREQ_800); minerva_change_freq(FREQ_800);
// Trim table.
int entries = 0;
for (u32 i = 0; i < mtc_cfg->table_entries; i++)
{
// Copy freqs from 204 MHz to 800 MHz and 1600 MHz and above.
int rate = mtc_cfg->mtc_table[i].rate_khz;
if ((rate >= FREQ_204 && rate <= FREQ_800) || rate >= FREQ_1600)
{
memcpy(&mtc_cfg->mtc_table[entries], &mtc_cfg->mtc_table[i], sizeof(emc_table_t));
entries++;
}
}
mtc_cfg->table_entries = entries;
// Do not let other mtc ops. // Do not let other mtc ops.
mtc_cfg->init_done = 0; mtc_cfg->init_done = 0;
} }

3
bdk/mem/minerva.h
View File

@ -53,8 +53,9 @@ enum train_mode_t
typedef enum typedef enum
{ {
FREQ_204 = 204000, FREQ_204 = 204000,
FREQ_666 = 665600, FREQ_408 = 408000,
FREQ_800 = 800000, FREQ_800 = 800000,
FREQ_1333 = 1331200,
FREQ_1600 = 1600000 FREQ_1600 = 1600000
} minerva_freq_t; } minerva_freq_t;