diff --git a/bdk/display/di.c b/bdk/display/di.c
index b061c55..b495ffe 100644
--- a/bdk/display/di.c
+++ b/bdk/display/di.c
@@ -35,8 +35,8 @@
extern volatile nyx_storage_t *nyx_str;
-static u32 _display_id = 0;
-static bool nx_aula = false;
+static u32 _display_id = 0;
+static bool _nx_aula = false;
static void _display_panel_and_hw_end(bool no_panel_deinit);
@@ -362,7 +362,7 @@ void display_dsi_vblank_write(u8 cmd, u32 len, void *data)
void display_init()
{
// Get Hardware type, as it's used in various DI functions.
- nx_aula = fuse_read_hw_type() == FUSE_NX_HW_TYPE_AULA;
+ _nx_aula = fuse_read_hw_type() == FUSE_NX_HW_TYPE_AULA;
// Check if display is already initialized.
if (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & BIT(CLK_L_DISP1))
@@ -380,7 +380,6 @@ void display_init()
// Set slew rate and enable SD2 regulator.
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD2_CFG, (1 << MAX77620_SD_SR_SHIFT) | MAX77620_SD_CFG1_FSRADE_SD_ENABLE);
max7762x_regulator_enable(REGULATOR_SD2, true);
-
}
// Enable LCD DVDD.
@@ -393,7 +392,6 @@ void display_init()
// Enable Display Interface specific clocks.
CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI);
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI);
-
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1);
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1);
@@ -416,7 +414,7 @@ void display_init()
PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) &= ~PINMUX_TRISTATE; // PULL_DOWN | 1
PINMUX_AUX(PINMUX_AUX_LCD_BL_EN) &= ~PINMUX_TRISTATE; // PULL_DOWN
- if (nx_aula)
+ if (_nx_aula)
{
// Configure LCD RST pin.
gpio_config(GPIO_PORT_V, GPIO_PIN_2, GPIO_MODE_GPIO);
@@ -468,22 +466,26 @@ void display_init()
}
// Setup Display Interface initial window configuration.
- exec_cfg((u32 *)DISPLAY_A_BASE, _display_dc_setup_win_config, 94);
+ exec_cfg((u32 *)DISPLAY_A_BASE, _di_dc_setup_win_config, CFG_SIZE(_di_dc_setup_win_config));
- // Setup display communication interfaces.
- exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config_part1, 8);
+ // Setup dsi init sequence packets.
+ exec_cfg((u32 *)DSI_BASE, _di_dsi_init_irq_pkt_config0, CFG_SIZE(_di_dsi_init_irq_pkt_config0));
if (tegra_t210)
DSI(_DSIREG(DSI_INIT_SEQ_DATA_15)) = 0;
else
DSI(_DSIREG(DSI_INIT_SEQ_DATA_15_B01)) = 0;
- exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config_part2, 14);
+ exec_cfg((u32 *)DSI_BASE, _di_dsi_init_irq_pkt_config1, CFG_SIZE(_di_dsi_init_irq_pkt_config1));
+
+ // Reset pad trimmers for T210B01.
if (!tegra_t210)
- exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config_part3_t210b01, 7);
- exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config_part4, 10);
- DSI(_DSIREG(DSI_PHY_TIMING_0)) = tegra_t210 ? 0x6070601 : 0x6070603;
- exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config_part5, 12);
- DSI(_DSIREG(DSI_PHY_TIMING_0)) = tegra_t210 ? 0x6070601 : 0x6070603;
- exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config_part6, 14);
+ exec_cfg((u32 *)DSI_BASE, _di_dsi_init_pads_t210b01, CFG_SIZE(_di_dsi_init_pads_t210b01));
+
+ // Setup init sequence packets and timings.
+ exec_cfg((u32 *)DSI_BASE, _di_dsi_init_timing_pkt_config2, CFG_SIZE(_di_dsi_init_timing_pkt_config2));
+ DSI(_DSIREG(DSI_PHY_TIMING_0)) = tegra_t210 ? 0x6070601 : 0x6070603; // DSI_THSPREPR: 1 : 3.
+ exec_cfg((u32 *)DSI_BASE, _di_dsi_init_timing_pwrctrl_config, CFG_SIZE(_di_dsi_init_timing_pwrctrl_config));
+ DSI(_DSIREG(DSI_PHY_TIMING_0)) = tegra_t210 ? 0x6070601 : 0x6070603; // DSI_THSPREPR: 1 : 3.
+ exec_cfg((u32 *)DSI_BASE, _di_dsi_init_timing_pkt_config3, CFG_SIZE(_di_dsi_init_timing_pkt_config3));
usleep(10000);
// Enable LCD Reset.
@@ -491,7 +493,7 @@ void display_init()
usleep(60000);
// Setup DSI device takeover timeout.
- DSI(_DSIREG(DSI_BTA_TIMING)) = nx_aula ? 0x40103 : 0x50204;
+ DSI(_DSIREG(DSI_BTA_TIMING)) = _nx_aula ? 0x40103 : 0x50204;
// Get Display ID.
_display_id = 0xCCCCCC;
@@ -513,7 +515,7 @@ void display_init()
_display_id = PANEL_JDI_XXX062M;
// For Aula ensure that we have a compatible panel id.
- if (nx_aula && _display_id == 0xCCCC)
+ if (_nx_aula && _display_id == 0xCCCC)
_display_id = PANEL_SAM_AMS699VC01;
// Initialize display panel.
@@ -530,7 +532,7 @@ void display_init()
break;
case PANEL_JDI_XXX062M:
- exec_cfg((u32 *)DSI_BASE, _display_init_config_jdi, 43);
+ exec_cfg((u32 *)DSI_BASE, _di_dsi_panel_init_config_jdi, CFG_SIZE(_di_dsi_panel_init_config_jdi));
_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 180000);
break;
@@ -576,18 +578,21 @@ void display_init()
CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0;
CLOCK(CLK_RST_CONTROLLER_PLLD_MISC) = 0x2DFC00; // Use new PLLD_SDM_DIN.
- // Finalize DSI configuration.
+ // Finalize DSI init packet sequence configuration.
DSI(_DSIREG(DSI_PAD_CONTROL_1)) = 0;
DSI(_DSIREG(DSI_PHY_TIMING_0)) = tegra_t210 ? 0x6070601 : 0x6070603;
- exec_cfg((u32 *)DSI_BASE, _display_dsi_packet_config, 19);
- // Set pixel clock dividers: 234 / 3 / 1 = 78 MHz (offset) for 60 Hz.
+ exec_cfg((u32 *)DSI_BASE, _di_dsi_init_seq_pkt_final_config, CFG_SIZE(_di_dsi_init_seq_pkt_final_config));
+
+ // Set 1-by-1 pixel/clock and pixel clock to 234 / 3 = 78 MHz. For 60 Hz refresh rate.
DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4); // 4: div3.
- exec_cfg((u32 *)DSI_BASE, _display_dsi_mode_config, 10);
+
+ // Set DSI mode.
+ exec_cfg((u32 *)DSI_BASE, _di_dsi_mode_config, CFG_SIZE(_di_dsi_mode_config));
usleep(10000);
// Calibrate display communication pads.
- u32 loops = tegra_t210 ? 1 : 2; // Find out why this is done 2 times on Mariko.
- exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_pad_cal_config, 4);
+ u32 loops = tegra_t210 ? 1 : 2; // Calibrate pads 2 times on T210B01.
+ exec_cfg((u32 *)MIPI_CAL_BASE, _di_mipi_pad_cal_config, CFG_SIZE(_di_mipi_pad_cal_config));
for (u32 i = 0; i < loops; i++)
{
// Set MIPI bias pad config.
@@ -597,22 +602,22 @@ void display_init()
// Set pad trimmers and set MIPI DSI cal offsets.
if (tegra_t210)
{
- exec_cfg((u32 *)DSI_BASE, _display_dsi_pad_cal_config_t210, 4);
- exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_dsi_cal_offsets_config_t210, 4);
+ exec_cfg((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210, CFG_SIZE(_di_dsi_pad_cal_config_t210));
+ exec_cfg((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_offsets_config_t210, CFG_SIZE(_di_mipi_dsi_cal_offsets_config_t210));
}
else
{
- exec_cfg((u32 *)DSI_BASE, _display_dsi_pad_cal_config_t210b01, 7);
- exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_dsi_cal_offsets_config_t210b01, 4);
+ exec_cfg((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210b01, CFG_SIZE(_di_dsi_pad_cal_config_t210b01));
+ exec_cfg((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_offsets_config_t210b01, CFG_SIZE(_di_mipi_dsi_cal_offsets_config_t210b01));
}
- // Set the rest of MIPI cal offsets and apply calibration.
- exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_apply_dsi_cal_config, 12);
+ // Reset all MIPI cal offsets and start calibration.
+ exec_cfg((u32 *)MIPI_CAL_BASE, _di_mipi_start_dsi_cal_config, CFG_SIZE(_di_mipi_start_dsi_cal_config));
}
usleep(10000);
// Enable video display controller.
- exec_cfg((u32 *)DISPLAY_A_BASE, _display_video_disp_controller_enable_config, 113);
+ exec_cfg((u32 *)DISPLAY_A_BASE, _di_dc_video_enable_config, CFG_SIZE(_di_dc_video_enable_config));
}
void display_backlight_pwm_init()
@@ -703,8 +708,10 @@ static void _display_panel_and_hw_end(bool no_panel_deinit)
DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0;
// De-initialize video controller.
- exec_cfg((u32 *)DISPLAY_A_BASE, _display_video_disp_controller_disable_config, 17);
- exec_cfg((u32 *)DSI_BASE, _display_dsi_timing_deinit_config, 16);
+ exec_cfg((u32 *)DISPLAY_A_BASE, _di_dc_video_disable_config, CFG_SIZE(_di_dc_video_disable_config));
+
+ // Set timings for lowpower clocks.
+ exec_cfg((u32 *)DSI_BASE, _di_dsi_timing_deinit_config, CFG_SIZE(_di_dsi_timing_deinit_config));
if (_display_id != PANEL_SAM_AMS699VC01)
usleep(10000);
@@ -713,11 +720,11 @@ static void _display_panel_and_hw_end(bool no_panel_deinit)
switch (_display_id)
{
case PANEL_JDI_XXX062M:
- exec_cfg((u32 *)DSI_BASE, _display_deinit_config_jdi, 22);
+ exec_cfg((u32 *)DSI_BASE, _di_dsi_panel_deinit_config_jdi, CFG_SIZE(_di_dsi_panel_deinit_config_jdi));
break;
case PANEL_AUO_A062TAN01:
- exec_cfg((u32 *)DSI_BASE, _display_deinit_config_auo, 37);
+ exec_cfg((u32 *)DSI_BASE, _di_dsi_panel_deinit_config_auo, CFG_SIZE(_di_dsi_panel_deinit_config_auo));
break;
case PANEL_INL_2J055IA_27A:
@@ -766,7 +773,7 @@ skip_panel_deinit:
// Disable LCD power pins.
gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_LOW); // LCD Reset disable.
- if (!nx_aula) // HOS uses panel id.
+ if (!_nx_aula) // HOS uses panel id.
{
usleep(10000);
gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_LOW); // LCD AVDD -5.4V disable.
@@ -788,7 +795,7 @@ skip_panel_deinit:
DSI(_DSIREG(DSI_POWER_CONTROL)) = 0;
// Switch LCD PWM backlight pin to special function mode and enable PWM0 mode.
- if (!nx_aula)
+ if (!_nx_aula)
{
gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight PWM.
PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & ~PINMUX_TRISTATE) | PINMUX_TRISTATE;
@@ -806,7 +813,7 @@ u16 display_get_decoded_panel_id()
void display_set_decoded_panel_id(u32 id)
{
// Get Hardware type, as it's used in various DI functions.
- nx_aula = fuse_read_hw_type() == FUSE_NX_HW_TYPE_AULA;
+ _nx_aula = fuse_read_hw_type() == FUSE_NX_HW_TYPE_AULA;
// Decode Display ID.
_display_id = ((id >> 8) & 0xFF00) | (id & 0xFF);
@@ -815,13 +822,13 @@ void display_set_decoded_panel_id(u32 id)
_display_id = PANEL_JDI_XXX062M;
// For Aula ensure that we have a compatible panel id.
- if (nx_aula && _display_id == 0xCCCC)
+ if (_nx_aula && _display_id == 0xCCCC)
_display_id = PANEL_SAM_AMS699VC01;
}
void display_color_screen(u32 color)
{
- exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_one_color, 8);
+ exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_one_color, CFG_SIZE(_di_win_one_color));
// Configure display to show single color.
DISPLAY_A(_DIREG(DC_WIN_AD_WIN_OPTIONS)) = 0;
@@ -842,8 +849,8 @@ u32 *display_init_framebuffer_pitch()
// Sanitize framebuffer area.
memset((u32 *)IPL_FB_ADDRESS, 0, IPL_FB_SZ);
- // This configures the framebuffer @ IPL_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
- exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_pitch, 32);
+ // This configures the framebuffer @ IPL_FB_ADDRESS with a resolution of 720x1280 (line stride 720).
+ exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_framebuffer_pitch, CFG_SIZE(_di_win_framebuffer_pitch));
//usleep(35000); // Wait 2 frames. No need on Aula.
return (u32 *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR));
@@ -851,8 +858,8 @@ u32 *display_init_framebuffer_pitch()
u32 *display_init_framebuffer_pitch_inv()
{
- // This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
- exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_pitch_inv, 34);
+ // This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 720x1280 (line stride 720).
+ exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_framebuffer_pitch_inv, CFG_SIZE(_di_win_framebuffer_pitch_inv));
usleep(35000); // Wait 2 frames. No need on Aula.
return (u32 *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR));
@@ -860,8 +867,8 @@ u32 *display_init_framebuffer_pitch_inv()
u32 *display_init_framebuffer_block()
{
- // This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
- exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_block, 34);
+ // This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 720x1280.
+ exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_framebuffer_block, CFG_SIZE(_di_win_framebuffer_block));
usleep(35000); // Wait 2 frames. No need on Aula.
return (u32 *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR));
@@ -870,7 +877,7 @@ u32 *display_init_framebuffer_block()
u32 *display_init_framebuffer_log()
{
// This configures the framebuffer @ LOG_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
- exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_log, 20);
+ exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_framebuffer_log, CFG_SIZE(_di_win_framebuffer_log));
return (u32 *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR));
}
diff --git a/bdk/display/di.h b/bdk/display/di.h
index ad4ab1e..62aaf4f 100644
--- a/bdk/display/di.h
+++ b/bdk/display/di.h
@@ -43,13 +43,17 @@
// DC_CMD non-shadowed command/sync registers.
#define DC_CMD_GENERAL_INCR_SYNCPT 0x00
+#define SYNCPT_GENERAL_INDX(x) (((x) & 0xff) << 0)
+#define SYNCPT_GENERAL_COND(x) (((x) & 0xff) << 8)
+#define COND_REG_WR_SAFE 3
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x01
#define SYNCPT_CNTRL_SOFT_RESET BIT(0)
#define SYNCPT_CNTRL_NO_STALL BIT(8)
#define DC_CMD_CONT_SYNCPT_VSYNC 0x28
-#define SYNCPT_VSYNC_ENABLE BIT(8)
+#define SYNCPT_VSYNC_INDX(x) (((x) & 0xff) << 0)
+#define SYNCPT_VSYNC_ENABLE BIT(8)
#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
@@ -98,7 +102,13 @@
#define WINDOW_C_SELECT BIT(6)
#define WINDOW_D_SELECT BIT(7)
-#define DC_CMD_REG_ACT_CONTROL 0x043
+#define DC_CMD_REG_ACT_CONTROL 0x43
+#define GENERAL_ACT_HCNTR_SEL BIT(0)
+#define WIN_A_ACT_HCNTR_SEL BIT(2)
+#define WIN_B_ACT_HCNTR_SEL BIT(4)
+#define WIN_C_ACT_HCNTR_SEL BIT(6)
+#define CURSOR_ACT_HCNTR_SEL BIT(7)
+#define WIN_D_ACT_HCNTR_SEL BIT(10)
// DC_D_WIN_DD window D instance of DC_WIN
#define DC_D_WIN_DD_WIN_OPTIONS 0x80
@@ -124,6 +134,7 @@
#define DC_COM_CRC_CONTROL 0x300
#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
+#define LSC0_OUTPUT_POLARITY_LOW BIT(24)
#define DC_COM_DSC_TOP_CTL 0x33E
@@ -139,12 +150,29 @@
#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
+
#define DC_DISP_DISP_TIMING_OPTIONS 0x405
+#define VSYNC_H_POSITION(x) (((x) & 0x1fff) << 0)
+
#define DC_DISP_REF_TO_SYNC 0x406
+#define H_REF_TO_SYNC(x) (((x) & 0x1fff) << 0) // Min 0 pixel clock.
+#define V_REF_TO_SYNC(x) (((x) & 0x1fff) << 16) // Min 1 line clock.
+
#define DC_DISP_SYNC_WIDTH 0x407
+#define H_SYNC_WIDTH(x) (((x) & 0x1fff) << 0) // Min 1 pixel clock.
+#define V_SYNC_WIDTH(x) (((x) & 0x1fff) << 16) // Min 1 line clock.
+
#define DC_DISP_BACK_PORCH 0x408
+#define H_BACK_PORCH(x) (((x) & 0x1fff) << 0)
+#define V_BACK_PORCH(x) (((x) & 0x1fff) << 16)
+
#define DC_DISP_ACTIVE 0x409
+#define H_DISP_ACTIVE(x) (((x) & 0x1fff) << 0) // Min 16 pixel clock.
+#define V_DISP_ACTIVE(x) (((x) & 0x1fff) << 16) // Min 16 line clock.
+
#define DC_DISP_FRONT_PORCH 0x40A
+#define H_FRONT_PORCH(x) (((x) & 0x1fff) << 0) // Min -=PS_=-H_REF_TO_SYNC + 1
+#define V_FRONT_PORCH(x) (((x) & 0x1fff) << 16) // Min -=PS_=-V_REF_TO_SYNC + 1
#define DC_DISP_DISP_CLOCK_CONTROL 0x42E
#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
@@ -239,6 +267,10 @@
#define DC_DISP_SD_BL_CONTROL 0x4DC
#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4
+#define DC_WINC_COLOR_PALETTE 0x500
+#define DC_WINC_COLOR_PALETTE_IDX(off) (DC_WINC_COLOR_PALETTE + (off))
+#define DC_WINC_PALETTE_COLOR_EXT 0x600
+
#define DC_WIN_CSC_YOF 0x611
#define DC_WIN_CSC_KYRGB 0x612
#define DC_WIN_CSC_KUR 0x613
@@ -253,12 +285,13 @@
// The following registers are A/B/C shadows of the 0xB80/0xD80/0xF80 registers (see DISPLAY_WINDOW_HEADER).
#define DC_WIN_WIN_OPTIONS 0x700
-#define H_DIRECTION BIT(0)
-#define V_DIRECTION BIT(2)
-#define SCAN_COLUMN BIT(4)
-#define COLOR_EXPAND BIT(6)
-#define CSC_ENABLE BIT(18)
-#define WIN_ENABLE BIT(30)
+#define H_DIRECTION BIT(0)
+#define V_DIRECTION BIT(2)
+#define SCAN_COLUMN BIT(4)
+#define COLOR_EXPAND BIT(6)
+#define COLOR_PALETTE_ENABLE BIT(16)
+#define CSC_ENABLE BIT(18)
+#define WIN_ENABLE BIT(30)
#define DC_WIN_BUFFER_CONTROL 0x702
#define BUFFER_CONTROL_HOST 0
@@ -290,10 +323,22 @@
#define WIN_COLOR_DEPTH_YUV422R 0x17
#define WIN_COLOR_DEPTH_YCbCr422RA 0x18
#define WIN_COLOR_DEPTH_YUV422RA 0x19
+#define WIN_COLOR_DEPTH_YCbCr444P 0x29
+#define WIN_COLOR_DEPTH_YCrCb420SP 0x2A
+#define WIN_COLOR_DEPTH_YCbCr420SP 0x2B
+#define WIN_COLOR_DEPTH_YCrCb422SP 0x2C
+#define WIN_COLOR_DEPTH_YCbCr422SP 0x2D
+#define WIN_COLOR_DEPTH_YUV444P 0x34
+#define WIN_COLOR_DEPTH_YVU420SP 0x35
+#define WIN_COLOR_DEPTH_YUV420SP 0x36
+#define WIN_COLOR_DEPTH_YVU422SP 0x37
+#define WIN_COLOR_DEPTH_YUV422SP 0x38
+#define WIN_COLOR_DEPTH_YVU444SP 0x3B
+#define WIN_COLOR_DEPTH_YUV444SP 0x3C
#define DC_WIN_POSITION 0x704
-#define H_POSITION(x) (((x) & 0xFfff) << 0)
-#define V_POSITION(x) (((x) & 0x1fff) << 16)
+#define H_POSITION(x) (((x) & 0xffff) << 0) // Support negative.
+#define V_POSITION(x) (((x) & 0xffff) << 16) // Support negative.
#define DC_WIN_SIZE 0x705
#define H_SIZE(x) (((x) & 0x1fff) << 0)
@@ -316,6 +361,7 @@
#define DC_WIN_DV_CONTROL 0x70E
#define DC_WINBUF_BLEND_LAYER_CONTROL 0x716
+#define WIN_BLEND_DEPTH(x) (((x) & 0xff) << 0)
#define WIN_K1(x) (((x) & 0xff) << 8)
#define WIN_K2(x) (((x) & 0xff) << 16)
#define WIN_BLEND_ENABLE (0 << 24)
@@ -386,6 +432,7 @@
#define DSI_HOST_CONTROL_FIFO_SEL BIT(4)
#define DSI_HOST_CONTROL_HS BIT(5)
#define DSI_HOST_CONTROL_RAW BIT(6)
+#define DSI_HOST_CONTROL_TX_TRIG_MASK (3 << 12)
#define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12)
#define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12)
#define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12)
@@ -433,10 +480,14 @@
#define DSI_PKT_SEQ_5_LO 0x2D
#define DSI_PKT_SEQ_5_HI 0x2E
#define DSI_DCS_CMDS 0x33
+
#define DSI_PKT_LEN_0_1 0x34
#define DSI_PKT_LEN_2_3 0x35
#define DSI_PKT_LEN_4_5 0x36
#define DSI_PKT_LEN_6_7 0x37
+#define PKT0_LEN(x) (((x) & 0xffff) << 0)
+#define PKT1_LEN(x) (((x) & 0xffff) << 16)
+
#define DSI_PHY_TIMING_0 0x3C
#define DSI_PHY_TIMING_1 0x3D
#define DSI_PHY_TIMING_2 0x3E
@@ -726,7 +777,7 @@ void display_backlight(bool enable);
void display_backlight_brightness(u32 brightness, u32 step_delay);
u32 display_get_backlight_brightness();
-/*! Init display in full 1280x720 resolution (B8G8R8A8, line stride 768, framebuffer size = 1280*768*4 bytes). */
+/*! Init display in full 720x1280 resolution (B8G8R8A8, line stride 720, framebuffer size = 720*1280*4 bytes). */
u32 *display_init_framebuffer_pitch();
u32 *display_init_framebuffer_pitch_inv();
u32 *display_init_framebuffer_block();
diff --git a/bdk/display/di.inl b/bdk/display/di.inl
index c1e5d84..efe1716 100644
--- a/bdk/display/di.inl
+++ b/bdk/display/di.inl
@@ -15,8 +15,8 @@
* along with this program. If not, see .
*/
-//Display A config.
-static const cfg_op_t _display_dc_setup_win_config[94] = {
+// Display A config.
+static const cfg_op_t _di_dc_setup_win_config[] = {
{DC_CMD_STATE_ACCESS, 0},
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
@@ -119,18 +119,18 @@ static const cfg_op_t _display_dc_setup_win_config[94] = {
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}
};
-//DSI Init config.
-static const cfg_op_t _display_dsi_init_config_part1[8] = {
+// DSI Init config.
+static const cfg_op_t _di_dsi_init_irq_pkt_config0[] = {
{DSI_WR_DATA, 0},
{DSI_INT_ENABLE, 0},
{DSI_INT_STATUS, 0},
- {DSI_INT_MASK, 0},
+ {DSI_INT_MASK, 0},
{DSI_INIT_SEQ_DATA_0, 0},
{DSI_INIT_SEQ_DATA_1, 0},
{DSI_INIT_SEQ_DATA_2, 0},
{DSI_INIT_SEQ_DATA_3, 0}
};
-static const cfg_op_t _display_dsi_init_config_part2[14] = {
+static const cfg_op_t _di_dsi_init_irq_pkt_config1[] = {
{DSI_DCS_CMDS, 0},
{DSI_PKT_SEQ_0_LO, 0},
{DSI_PKT_SEQ_1_LO, 0},
@@ -146,7 +146,7 @@ static const cfg_op_t _display_dsi_init_config_part2[14] = {
{DSI_PKT_SEQ_5_HI, 0},
{DSI_CONTROL, 0}
};
-static const cfg_op_t _display_dsi_init_config_part3_t210b01[7] = {
+static const cfg_op_t _di_dsi_init_pads_t210b01[] = {
{DSI_PAD_CONTROL_1, 0},
{DSI_PAD_CONTROL_2, 0},
{DSI_PAD_CONTROL_3, 0},
@@ -155,10 +155,10 @@ static const cfg_op_t _display_dsi_init_config_part3_t210b01[7] = {
{DSI_PAD_CONTROL_6_B01, 0},
{DSI_PAD_CONTROL_7_B01, 0}
};
-static const cfg_op_t _display_dsi_init_config_part4[10] = {
+static const cfg_op_t _di_dsi_init_timing_pkt_config2[] = {
{DSI_PAD_CONTROL_CD, 0},
- {DSI_SOL_DELAY, 0x18},
- {DSI_MAX_THRESHOLD, 0x1E0},
+ {DSI_SOL_DELAY, 24},
+ {DSI_MAX_THRESHOLD, 480},
{DSI_TRIGGER, 0},
{DSI_INIT_SEQ_CONTROL, 0},
{DSI_PKT_LEN_0_1, 0},
@@ -167,12 +167,12 @@ static const cfg_op_t _display_dsi_init_config_part4[10] = {
{DSI_PKT_LEN_6_7, 0},
{DSI_PAD_CONTROL_1, 0}
};
-static const cfg_op_t _display_dsi_init_config_part5[12] = {
+static const cfg_op_t _di_dsi_init_timing_pwrctrl_config[] = {
{DSI_PHY_TIMING_1, 0x40A0E05},
{DSI_PHY_TIMING_2, 0x30109},
- {DSI_BTA_TIMING, 0x190A14},
+ {DSI_BTA_TIMING, 0x190A14},
{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
- {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)},
+ {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)},
{DSI_TO_TALLY, 0},
{DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)}, // Enable
{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
@@ -181,25 +181,25 @@ static const cfg_op_t _display_dsi_init_config_part5[12] = {
{DSI_POWER_CONTROL, 0},
{DSI_PAD_CONTROL_1, 0}
};
-static const cfg_op_t _display_dsi_init_config_part6[14] = {
+static const cfg_op_t _di_dsi_init_timing_pkt_config3[] = {
{DSI_PHY_TIMING_1, 0x40A0E05},
{DSI_PHY_TIMING_2, 0x30118},
- {DSI_BTA_TIMING, 0x190A14},
+ {DSI_BTA_TIMING, 0x190A14},
{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
- {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)},
+ {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)},
{DSI_TO_TALLY, 0},
{DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
{DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE},
{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
- {DSI_MAX_THRESHOLD, 0x40},
+ {DSI_MAX_THRESHOLD, 64},
{DSI_TRIGGER, 0},
{DSI_TX_CRC, 0},
{DSI_INIT_SEQ_CONTROL, 0}
};
-//DSI panel config.
-static const cfg_op_t _display_init_config_jdi[43] = {
+// DSI panel JDI config.
+static const cfg_op_t _di_dsi_panel_init_config_jdi[] = {
{DSI_WR_DATA, 0x0439}, // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
{DSI_WR_DATA, 0x9483FFB9}, // MIPI_DCS_PRIV_SET_EXTC. (Pass: FF 83 94).
{DSI_TRIGGER, DSI_TRIGGER_HOST},
@@ -245,13 +245,13 @@ static const cfg_op_t _display_init_config_jdi[43] = {
{DSI_TRIGGER, DSI_TRIGGER_HOST}
};
-//DSI packet config.
-static const cfg_op_t _display_dsi_packet_config[19] = {
+// DSI packet config.
+static const cfg_op_t _di_dsi_init_seq_pkt_final_config[] = {
{DSI_PHY_TIMING_1, 0x40A0E05},
{DSI_PHY_TIMING_2, 0x30172},
- {DSI_BTA_TIMING, 0x190A14},
+ {DSI_BTA_TIMING, 0x190A14},
{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)},
- {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)},
+ {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)},
{DSI_TO_TALLY, 0},
{DSI_PKT_SEQ_0_LO, 0x40000208},
{DSI_PKT_SEQ_2_LO, 0x40000308},
@@ -261,66 +261,66 @@ static const cfg_op_t _display_dsi_packet_config[19] = {
{DSI_PKT_SEQ_3_HI, 0x2CC},
{DSI_PKT_SEQ_5_LO, 0x3F3B2B08},
{DSI_PKT_SEQ_5_HI, 0x2CC},
- {DSI_PKT_LEN_0_1, 0xCE0000},
- {DSI_PKT_LEN_2_3, 0x87001A2},
- {DSI_PKT_LEN_4_5, 0x190},
- {DSI_PKT_LEN_6_7, 0x190},
+ {DSI_PKT_LEN_0_1, PKT1_LEN(206) | PKT0_LEN(0)},
+ {DSI_PKT_LEN_2_3, PKT1_LEN(2160) | PKT0_LEN(418)},
+ {DSI_PKT_LEN_4_5, PKT1_LEN(0) | PKT0_LEN(400)},
+ {DSI_PKT_LEN_6_7, PKT1_LEN(0) | PKT0_LEN(400)},
{DSI_HOST_CONTROL, 0}
};
-//DSI mode config.
-static const cfg_op_t _display_dsi_mode_config[10] = {
+// DSI mode config.
+static const cfg_op_t _di_dsi_mode_config[] = {
{DSI_TRIGGER, 0},
{DSI_CONTROL, 0},
{DSI_SOL_DELAY, 6},
- {DSI_MAX_THRESHOLD, 0x1E0},
+ {DSI_MAX_THRESHOLD, 480},
{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
{DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE},
- {DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL| DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
+ {DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
{DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE},
- {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
- {DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}
+ {DSI_HOST_CONTROL, DSI_HOST_CONTROL_TX_TRIG_SOL | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
+ {DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_TX_TRIG_SOL | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}
};
-//MIPI CAL config.
-static const cfg_op_t _display_mipi_pad_cal_config[4] = {
+// MIPI CAL config.
+static const cfg_op_t _di_mipi_pad_cal_config[] = {
{MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0},
{MIPI_CAL_CIL_MIPI_CAL_STATUS, 0xF3F10000},
{MIPI_CAL_MIPI_BIAS_PAD_CFG0, 0},
{MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0}
};
-//DSI config.
-static const cfg_op_t _display_dsi_pad_cal_config_t210[4] = {
+// DSI pad config.
+static const cfg_op_t _di_dsi_pad_cal_config_t210[] = {
{DSI_PAD_CONTROL_1, 0},
{DSI_PAD_CONTROL_2, 0},
{DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)},
{DSI_PAD_CONTROL_4, 0}
};
-static const cfg_op_t _display_dsi_pad_cal_config_t210b01[7] = {
- {DSI_PAD_CONTROL_1, 0},
- {DSI_PAD_CONTROL_2, 0},
- {DSI_PAD_CONTROL_3, 0},
- {DSI_PAD_CONTROL_4, 0x77777},
+static const cfg_op_t _di_dsi_pad_cal_config_t210b01[] = {
+ {DSI_PAD_CONTROL_1, 0},
+ {DSI_PAD_CONTROL_2, 0},
+ {DSI_PAD_CONTROL_3, 0},
+ {DSI_PAD_CONTROL_4, 0x77777},
{DSI_PAD_CONTROL_5_B01, 0x77777},
{DSI_PAD_CONTROL_6_B01, 0x1111},
{DSI_PAD_CONTROL_7_B01, 0}
};
-//MIPI CAL config.
-static const cfg_op_t _display_mipi_dsi_cal_offsets_config_t210[4] = {
+// MIPI CAL config.
+static const cfg_op_t _di_mipi_dsi_cal_offsets_config_t210[] = {
{MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200200},
{MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200200},
{MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x200002},
{MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x200002}
};
-static const cfg_op_t _display_mipi_dsi_cal_offsets_config_t210b01[4] = {
+static const cfg_op_t _di_mipi_dsi_cal_offsets_config_t210b01[] = {
{MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200006},
{MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200006},
{MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x260000},
{MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x260000}
};
-static const cfg_op_t _display_mipi_apply_dsi_cal_config[12] = {
+static const cfg_op_t _di_mipi_start_dsi_cal_config[] = {
{MIPI_CAL_CILA_MIPI_CAL_CONFIG, 0},
{MIPI_CAL_CILB_MIPI_CAL_CONFIG, 0},
{MIPI_CAL_CILC_MIPI_CAL_CONFIG, 0},
@@ -332,11 +332,11 @@ static const cfg_op_t _display_mipi_apply_dsi_cal_config[12] = {
{MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0},
{MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2, 0},
{MIPI_CAL_DSID_MIPI_CAL_CONFIG_2, 0},
- {MIPI_CAL_MIPI_CAL_CTRL, 0x2A000001}
+ {MIPI_CAL_MIPI_CAL_CTRL, 0x2A000001} // Set Prescale and filter and start calibration.
};
-//Display A config.
-static const cfg_op_t _display_video_disp_controller_enable_config[113] = {
+// Display A enable config.
+static const cfg_op_t _di_dc_video_enable_config[] = {
{DC_CMD_STATE_ACCESS, 0},
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{DC_WIN_WIN_OPTIONS, 0},
@@ -397,7 +397,7 @@ static const cfg_op_t _display_video_disp_controller_enable_config[113] = {
{DC_WIN_WIN_OPTIONS, 0},
{DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
{DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
- {DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000},
+ {DC_COM_PIN_OUTPUT_POLARITY(1), LSC0_OUTPUT_POLARITY_LOW},
{DC_COM_PIN_OUTPUT_POLARITY(3), 0},
{DC_DISP_BLEND_BACKGROUND_COLOR, 0},
{DC_COM_CRC_CONTROL, 0},
@@ -422,34 +422,13 @@ static const cfg_op_t _display_video_disp_controller_enable_config[113] = {
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
{DC_CMD_STATE_ACCESS, 0},
- /* Set Display timings
- *
- * DC_DISP_REF_TO_SYNC:
- * V_REF_TO_SYNC - 1
- * H_REF_TO_SYNC - 0
- *
- * DC_DISP_SYNC_WIDTH:
- * V_SYNC_WIDTH - 1
- * H_SYNC_WIDTH - 72
- *
- * DC_DISP_BACK_PORCH:
- * V_BACK_PORCH - 9
- * H_BACK_PORCH - 72
- *
- * DC_DISP_ACTIVE:
- * V_DISP_ACTIVE - 1280
- * H_DISP_ACTIVE - 720
- *
- * DC_DISP_FRONT_PORCH:
- * V_FRONT_PORCH - 10
- * H_FRONT_PORCH - 136
- */
- {DC_DISP_DISP_TIMING_OPTIONS, 0},
- {DC_DISP_REF_TO_SYNC, 0x10000},
- {DC_DISP_SYNC_WIDTH, 0x10048},
- {DC_DISP_BACK_PORCH, 0x90048},
- {DC_DISP_ACTIVE, 0x50002D0},
- {DC_DISP_FRONT_PORCH, 0xA0088}, // Sources say that this should happen before DC_DISP_ACTIVE cmd.
+ /* Set panel timings */
+ {DC_DISP_DISP_TIMING_OPTIONS, VSYNC_H_POSITION(0)},
+ {DC_DISP_REF_TO_SYNC, V_REF_TO_SYNC(1) | H_REF_TO_SYNC(0)},
+ {DC_DISP_SYNC_WIDTH, V_SYNC_WIDTH(1) | H_SYNC_WIDTH(72)},
+ {DC_DISP_BACK_PORCH, V_BACK_PORCH(9) | H_BACK_PORCH(72)},
+ {DC_DISP_FRONT_PORCH, V_FRONT_PORCH(10) | H_FRONT_PORCH(136)},
+ {DC_DISP_ACTIVE, V_DISP_ACTIVE(1280) | H_DISP_ACTIVE(720)},
/* End of Display timings */
{DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE},
@@ -469,7 +448,7 @@ static const cfg_op_t _display_video_disp_controller_enable_config[113] = {
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
{DC_CMD_STATE_ACCESS, READ_MUX | WRITE_MUX},
- {DC_DISP_FRONT_PORCH, 0xA0088},
+ {DC_DISP_FRONT_PORCH, V_FRONT_PORCH(10) | H_FRONT_PORCH(136)},
{DC_CMD_STATE_ACCESS, 0},
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
@@ -483,9 +462,9 @@ static const cfg_op_t _display_video_disp_controller_enable_config[113] = {
{DC_CMD_DISPLAY_COMMAND_OPTION0, 0}
};
-////Display A config.
-static const cfg_op_t _display_video_disp_controller_disable_config[17] = {
- {DC_DISP_FRONT_PORCH, 0xA0088},
+// Display A disable config.
+static const cfg_op_t _di_dc_video_disable_config[] = {
+ {DC_DISP_FRONT_PORCH, V_FRONT_PORCH(10) | H_FRONT_PORCH(136)},
{DC_CMD_INT_MASK, 0},
{DC_CMD_STATE_ACCESS, 0},
{DC_CMD_INT_ENABLE, 0},
@@ -504,28 +483,28 @@ static const cfg_op_t _display_video_disp_controller_disable_config[17] = {
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
};
-//DSI config.
-static const cfg_op_t _display_dsi_timing_deinit_config[16] = {
+// DSI deinit config.
+static const cfg_op_t _di_dsi_timing_deinit_config[] = {
{DSI_POWER_CONTROL, 0},
{DSI_PAD_CONTROL_1, 0},
{DSI_PHY_TIMING_0, 0x6070601},
{DSI_PHY_TIMING_1, 0x40A0E05},
{DSI_PHY_TIMING_2, 0x30118},
- {DSI_BTA_TIMING, 0x190A14},
+ {DSI_BTA_TIMING, 0x190A14},
{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF) },
- {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)},
+ {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)},
{DSI_TO_TALLY, 0},
{DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
{DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE},
{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
- {DSI_MAX_THRESHOLD, 0x40},
+ {DSI_MAX_THRESHOLD, 64},
{DSI_TRIGGER, 0},
{DSI_TX_CRC, 0},
{DSI_INIT_SEQ_CONTROL, 0}
};
-//DSI config (if ver == 0x10).
-static const cfg_op_t _display_deinit_config_jdi[22] = {
+// DSI panel JDI deinit config.
+static const cfg_op_t _di_dsi_panel_deinit_config_jdi[] = {
{DSI_WR_DATA, 0x439}, // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
{DSI_WR_DATA, 0x9483FFB9}, // MIPI_DCS_PRIV_SET_EXTC. (Pass: FF 83 94).
{DSI_TRIGGER, DSI_TRIGGER_HOST},
@@ -550,7 +529,8 @@ static const cfg_op_t _display_deinit_config_jdi[22] = {
{DSI_TRIGGER, DSI_TRIGGER_HOST}
};
-static const cfg_op_t _display_deinit_config_auo[37] = {
+// DSI panel AUO deinit config.
+static const cfg_op_t _di_dsi_panel_deinit_config_auo[] = {
{DSI_WR_DATA, 0x439}, // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
{DSI_WR_DATA, 0x9483FFB9}, // MIPI_DCS_PRIV_SET_EXTC. (Pass: FF 83 94).
{DSI_TRIGGER, DSI_TRIGGER_HOST},
@@ -591,14 +571,14 @@ static const cfg_op_t _display_deinit_config_auo[37] = {
{DSI_TRIGGER, DSI_TRIGGER_HOST}
};
-static const cfg_op_t _display_init_config_invert[3] = {
+static const cfg_op_t _di_init_config_invert[] = {
{DSI_WR_DATA, 0x239},
{DSI_WR_DATA, 0x02C1}, // INV_EN.
{DSI_TRIGGER, DSI_TRIGGER_HOST},
};
-//Display A config.
-static const cfg_op_t cfg_display_one_color[8] = {
+// Display A Window A one color config.
+static const cfg_op_t _di_win_one_color[] = {
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{DC_WIN_WIN_OPTIONS, 0},
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
@@ -609,8 +589,8 @@ static const cfg_op_t cfg_display_one_color[8] = {
{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY} // Continuous display.
};
-//Display A config linear pitch.
-static const cfg_op_t cfg_display_framebuffer_pitch[32] = {
+// Display A Window A linear pitch config.
+static const cfg_op_t _di_win_framebuffer_pitch[] = {
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{DC_WIN_WIN_OPTIONS, 0},
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
@@ -645,8 +625,8 @@ static const cfg_op_t cfg_display_framebuffer_pitch[32] = {
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ}
};
-//Display A config linear pitch inverse + Win D support.
-static const cfg_op_t cfg_display_framebuffer_pitch_inv[34] = {
+// Display A Window A linear pitch inverse + Win D support config.
+static const cfg_op_t _di_win_framebuffer_pitch_inv[] = {
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_D_SELECT},
{DC_WIN_WIN_OPTIONS, 0},
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
@@ -683,8 +663,8 @@ static const cfg_op_t cfg_display_framebuffer_pitch_inv[34] = {
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ}
};
-//Display A config block linear.
-static const cfg_op_t cfg_display_framebuffer_block[34] = {
+// Display A Window A block linear config.
+static const cfg_op_t _di_win_framebuffer_block[] = {
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_D_SELECT},
{DC_WIN_WIN_OPTIONS, 0},
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
@@ -721,8 +701,8 @@ static const cfg_op_t cfg_display_framebuffer_block[34] = {
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ}
};
-//Display D config.
-static const cfg_op_t cfg_display_framebuffer_log[20] = {
+// Display A Window D config.
+static const cfg_op_t _di_win_framebuffer_log[] = {
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_D_SELECT},
{DC_WIN_WIN_OPTIONS, 0},
{DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8},
diff --git a/bdk/utils/util.h b/bdk/utils/util.h
index c4d0bb0..c22b78b 100644
--- a/bdk/utils/util.h
+++ b/bdk/utils/util.h
@@ -21,6 +21,8 @@
#include
#include
+#define CFG_SIZE(array) (sizeof(array) / sizeof(cfg_op_t))
+
#define NYX_NEW_INFO 0x3058594E
typedef enum