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bdk: small refactor

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CTCaer 2022-10-11 06:16:38 +03:00
parent 4f2a6f16d3
commit bfad719fcd
10 changed files with 186 additions and 121 deletions
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2
bdk/ianos/elfload/elf.h
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@ -445,7 +445,7 @@ typedef struct
/* Dynamic structure */ /* Dynamic structure */
typedef struct typedef struct
{ {
Elf32_Sword d_tag; /* controls meaning of d_val */ Elf32_Word d_tag; /* controls meaning of d_val */
union { union {
Elf32_Word d_val; /* Multiple meanings - see d_tag */ Elf32_Word d_val; /* Multiple meanings - see d_tag */
Elf32_Addr d_ptr; /* program virtual address */ Elf32_Addr d_ptr; /* program virtual address */

14
bdk/libs/lvgl/lv_misc/lv_color.h
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@ -412,17 +412,17 @@ static inline uint8_t lv_color_brightness(lv_color_t color)
#endif #endif
#if LV_COLOR_DEPTH == 32 // Concatenate into one 32-bit set. #if LV_COLOR_DEPTH == 32 // Concatenate into one 32-bit set.
#define LV_COLOR_HEX(c) ((lv_color_t){.full = (c | 0xFF000000)}) #define LV_COLOR_HEX(c) ((lv_color_t){.full = ((c) | 0xFF000000)})
#else #else
#define LV_COLOR_HEX(c) LV_COLOR_MAKE(((uint32_t)((uint32_t)c >> 16) & 0xFF), \ #define LV_COLOR_HEX(c) LV_COLOR_MAKE(((uint32_t)((uint32_t)(c) >> 16) & 0xFF), \
((uint32_t)((uint32_t)c >> 8) & 0xFF), \ ((uint32_t)((uint32_t)(c) >> 8) & 0xFF), \
((uint32_t) c & 0xFF)) ((uint32_t) (c) & 0xFF))
#endif #endif
/*Usage LV_COLOR_HEX3(0x16C) which means LV_COLOR_HEX(0x1166CC)*/ /*Usage LV_COLOR_HEX3(0x16C) which means LV_COLOR_HEX(0x1166CC)*/
#define LV_COLOR_HEX3(c) LV_COLOR_MAKE((((c >> 4) & 0xF0) | ((c >> 8) & 0xF)), \ #define LV_COLOR_HEX3(c) LV_COLOR_MAKE(((((c) >> 4) & 0xF0) | (((c) >> 8) & 0xF)), \
((uint32_t)(c & 0xF0) | ((c & 0xF0) >> 4)), \ ((uint32_t)((c) & 0xF0) | (((c) & 0xF0) >> 4)), \
((uint32_t)(c & 0xF) | ((c & 0xF) << 4))) ((uint32_t)((c) & 0xF) | (((c) & 0xF) << 4)))
/** /**

21
bdk/power/max77812.h
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@ -66,21 +66,22 @@
#define MAX77812_REG_M2_VOUT_S 0x2C #define MAX77812_REG_M2_VOUT_S 0x2C
#define MAX77812_REG_M3_VOUT_S 0x2D #define MAX77812_REG_M3_VOUT_S 0x2D
#define MAX77812_REG_M4_VOUT_S 0x2E #define MAX77812_REG_M4_VOUT_S 0x2E
#define MAX77812_REG_M1_CFG 0x2F #define MAX77812_REG_M1_CFG 0x2F // HOS: M1_ILIM - 7.2A/4.8A.
#define MAX77812_REG_M2_CFG 0x30 #define MAX77812_REG_M2_CFG 0x30 // HOS: M2_ILIM - 7.2A/4.8A.
#define MAX77812_REG_M3_CFG 0x31 #define MAX77812_REG_M3_CFG 0x31 // HOS: M3_ILIM - 7.2A/4.8A.
#define MAX77812_REG_M4_CFG 0x32 #define MAX77812_REG_M4_CFG 0x32 // HOS: M4_ILIM - 7.2A/4.8A.
#define MAX77812_REG_GLB_CFG1 0x33 #define MAX77812_REG_GLB_CFG1 0x33 // HOS: B_SD_SR/B_SS_SR - 5mV/ìs.
#define MAX77812_REG_GLB_CFG2 0x34 #define MAX77812_REG_GLB_CFG2 0x34 // HOS: B_RD_SR/B_RU_SR - 5mV/ìs
#define MAX77812_REG_GLB_CFG3 0x35 #define MAX77812_REG_GLB_CFG3 0x35
/*! Protected area and settings only for MAX77812_ES2_VERSION */ /*! Protected area and settings only for MAX77812_ES2_VERSION */
#define MAX77812_REG_GLB_CFG4 0x36 #define MAX77812_REG_GLB_CFG4 0x36
#define MAX77812_REG_GLB_CFG5 0x37 #define MAX77812_REG_GLB_CFG5 0x37 // HOS: 0x3E. Unmasked write.
#define MAX77812_REG_GLB_CFG6 0x38 #define MAX77812_REG_GLB_CFG6 0x38 // HOS: 0x90. Unmasked write.
#define MAX77812_REG_GLB_CFG7 0x39 #define MAX77812_REG_GLB_CFG7 0x39
#define MAX77812_REG_GLB_CFG8 0x3A #define MAX77812_REG_GLB_CFG8 0x3A // HOS: 0x3A. Unmasked write.
#define MAX77812_REG_PROT_ACCESS 0xFD
#define MAX77812_REG_PROT_ACCESS 0xFD // 0x00: Lock, 0x5A: Unlock.
#define MAX77812_REG_MAX 0xFD #define MAX77812_REG_MAX 0xFD
#define MAX77812_REG_EN_CTRL_MASK(n) BIT(n) #define MAX77812_REG_EN_CTRL_MASK(n) BIT(n)

12
bdk/rtc/max77620-rtc.c
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@ -1,7 +1,7 @@
/* /*
* PMIC Real Time Clock driver for Nintendo Switch's MAX77620-RTC * PMIC Real Time Clock driver for Nintendo Switch's MAX77620-RTC
* *
* Copyright (c) 2018-2019 CTCaer * Copyright (c) 2018-2022 CTCaer
* Copyright (c) 2019 shchmue * Copyright (c) 2019 shchmue
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
@ -19,7 +19,14 @@
#include <rtc/max77620-rtc.h> #include <rtc/max77620-rtc.h>
#include <soc/i2c.h> #include <soc/i2c.h>
#include <utils/util.h> #include <soc/pmc.h>
#include <soc/timer.h>
#include <soc/t210.h>
void max77620_rtc_prep_read()
{
i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_UPDATE0_REG, MAX77620_RTC_READ_UPDATE);
}
void max77620_rtc_get_time(rtc_time_t *time) void max77620_rtc_get_time(rtc_time_t *time)
{ {
@ -64,6 +71,7 @@ void max77620_rtc_stop_alarm()
// Update RTC regs from RTC clock. // Update RTC regs from RTC clock.
i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_UPDATE0_REG, MAX77620_RTC_READ_UPDATE); i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_UPDATE0_REG, MAX77620_RTC_READ_UPDATE);
msleep(16);
// Stop alarm for both ALARM1 and ALARM2. Horizon uses ALARM2. // Stop alarm for both ALARM1 and ALARM2. Horizon uses ALARM2.
for (int i = 0; i < (MAX77620_RTC_NR_TIME_REGS * 2); i++) for (int i = 0; i < (MAX77620_RTC_NR_TIME_REGS * 2); i++)

10
bdk/rtc/max77620-rtc.h
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@ -1,7 +1,7 @@
/* /*
* PMIC Real Time Clock driver for Nintendo Switch's MAX77620-RTC * PMIC Real Time Clock driver for Nintendo Switch's MAX77620-RTC
* *
* Copyright (c) 2018 CTCaer * Copyright (c) 2018-2022 CTCaer
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@ -25,6 +25,8 @@
#define MAX77620_RTC_NR_TIME_REGS 7 #define MAX77620_RTC_NR_TIME_REGS 7
#define MAX77620_RTC_RTCINT_REG 0x00
#define MAX77620_RTC_RTCINTM_REG 0x01
#define MAX77620_RTC_CONTROLM_REG 0x02 #define MAX77620_RTC_CONTROLM_REG 0x02
#define MAX77620_RTC_CONTROL_REG 0x03 #define MAX77620_RTC_CONTROL_REG 0x03
#define MAX77620_RTC_BIN_FORMAT BIT(0) #define MAX77620_RTC_BIN_FORMAT BIT(0)
@ -34,6 +36,9 @@
#define MAX77620_RTC_WRITE_UPDATE BIT(0) #define MAX77620_RTC_WRITE_UPDATE BIT(0)
#define MAX77620_RTC_READ_UPDATE BIT(4) #define MAX77620_RTC_READ_UPDATE BIT(4)
#define MAX77620_RTC_UPDATE1_REG 0x05
#define MAX77620_RTC_RTCSMPL_REG 0x06
#define MAX77620_RTC_SEC_REG 0x07 #define MAX77620_RTC_SEC_REG 0x07
#define MAX77620_RTC_MIN_REG 0x08 #define MAX77620_RTC_MIN_REG 0x08
#define MAX77620_RTC_HOUR_REG 0x09 #define MAX77620_RTC_HOUR_REG 0x09
@ -69,9 +74,10 @@ typedef struct _rtc_time_t {
u16 year; u16 year;
} rtc_time_t; } rtc_time_t;
void max77620_rtc_prep_read();
void max77620_rtc_get_time(rtc_time_t *time); void max77620_rtc_get_time(rtc_time_t *time);
void max77620_rtc_stop_alarm(); void max77620_rtc_stop_alarm();
void max77620_rtc_epoch_to_date(u32 epoch, rtc_time_t *time); void max77620_rtc_epoch_to_date(u32 epoch, rtc_time_t *time);
u32 max77620_rtc_date_to_epoch(const rtc_time_t *time); u32 max77620_rtc_date_to_epoch(const rtc_time_t *time);
#endif /* _MFD_MAX77620_RTC_H_ */ #endif /* _MFD_MAX77620_RTC_H_ */

2
bdk/soc/fuse.h
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@ -90,7 +90,7 @@ enum
FUSE_NX_HW_TYPE_ICOSA, FUSE_NX_HW_TYPE_ICOSA,
FUSE_NX_HW_TYPE_IOWA, FUSE_NX_HW_TYPE_IOWA,
FUSE_NX_HW_TYPE_HOAG, FUSE_NX_HW_TYPE_HOAG,
FUSE_NX_HW_TYPE_AULA FUSE_NX_HW_TYPE_AULA
}; };
enum enum

4
bdk/soc/hw_init.c
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@ -141,7 +141,7 @@ static void _config_gpios(bool nx_hoag)
static void _config_pmc_scratch() static void _config_pmc_scratch()
{ {
PMC(APBDEV_PMC_SCRATCH20) &= 0xFFF3FFFF; // Unset Debug console from Customer Option. PMC(APBDEV_PMC_SCRATCH20) &= 0xFFF3FFFF; // Unset Debug console from Customer Option.
PMC(APBDEV_PMC_SCRATCH190) &= 0xFFFFFFFE; // Unset DATA_DQ_E_IVREF EMC_PMACRO_DATA_PAD_TX_CTRL PMC(APBDEV_PMC_SCRATCH190) &= 0xFFFFFFFE; // Unset WDT_DURING_BR.
PMC(APBDEV_PMC_SECURE_SCRATCH21) |= PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT; PMC(APBDEV_PMC_SECURE_SCRATCH21) |= PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT;
} }
@ -259,7 +259,7 @@ static void _config_se_brom()
// se_key_acc_ctrl(15, SE_KEY_TBL_DIS_KEYREAD_FLAG); // se_key_acc_ctrl(15, SE_KEY_TBL_DIS_KEYREAD_FLAG);
// This memset needs to happen here, else TZRAM will behave weirdly later on. // This memset needs to happen here, else TZRAM will behave weirdly later on.
memset((void *)TZRAM_BASE, 0, SZ_64K); memset((void *)TZRAM_BASE, 0, TZRAM_SIZE);
PMC(APBDEV_PMC_CRYPTO_OP) = PMC_CRYPTO_OP_SE_ENABLE; PMC(APBDEV_PMC_CRYPTO_OP) = PMC_CRYPTO_OP_SE_ENABLE;
SE(SE_INT_STATUS_REG) = 0x1F; // Clear all SE interrupts. SE(SE_INT_STATUS_REG) = 0x1F; // Clear all SE interrupts.

2
bdk/soc/pinmux.h
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@ -126,6 +126,8 @@
#define PINMUX_DRIVE_3X (2 << 13) #define PINMUX_DRIVE_3X (2 << 13)
#define PINMUX_DRIVE_4X (3 << 13) #define PINMUX_DRIVE_4X (3 << 13)
#define PINMUX_PREEMP BIT(15)
void pinmux_config_uart(u32 idx); void pinmux_config_uart(u32 idx);
void pinmux_config_i2c(u32 idx); void pinmux_config_i2c(u32 idx);

38
bdk/soc/pmc.h
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@ -40,23 +40,24 @@
#define APBDEV_PMC_PWRGATE_STATUS 0x38 #define APBDEV_PMC_PWRGATE_STATUS 0x38
#define APBDEV_PMC_NO_IOPOWER 0x44 #define APBDEV_PMC_NO_IOPOWER 0x44
#define PMC_NO_IOPOWER_SDMMC1_IO_EN BIT(12) #define PMC_NO_IOPOWER_SDMMC1_IO_EN BIT(12)
#define PMC_NO_IOPOWER_SDMMC4_IO_EN BIT(14)
#define PMC_NO_IOPOWER_AUDIO_HV BIT(18) #define PMC_NO_IOPOWER_AUDIO_HV BIT(18)
#define PMC_NO_IOPOWER_GPIO_IO_EN BIT(21) #define PMC_NO_IOPOWER_GPIO_IO_EN BIT(21)
#define APBDEV_PMC_SCRATCH0 0x50 #define APBDEV_PMC_SCRATCH0 0x50
#define PMC_SCRATCH0_MODE_WARMBOOT BIT(0) #define PMC_SCRATCH0_MODE_WARMBOOT BIT(0)
#define PMC_SCRATCH0_MODE_RCM BIT(1) #define PMC_SCRATCH0_MODE_RCM BIT(1)
#define PMC_SCRATCH0_MODE_PAYLOAD BIT(29) #define PMC_SCRATCH0_MODE_PAYLOAD BIT(29)
#define PMC_SCRATCH0_MODE_FASTBOOT BIT(30) #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
#define PMC_SCRATCH0_MODE_RECOVERY BIT(31) #define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
#define PMC_SCRATCH0_MODE_CUSTOM_ALL (PMC_SCRATCH0_MODE_RECOVERY | \ #define PMC_SCRATCH0_MODE_CUSTOM_ALL (PMC_SCRATCH0_MODE_RECOVERY | \
PMC_SCRATCH0_MODE_FASTBOOT | \ PMC_SCRATCH0_MODE_BOOTLOADER | \
PMC_SCRATCH0_MODE_PAYLOAD) PMC_SCRATCH0_MODE_PAYLOAD)
#define APBDEV_PMC_BLINK_TIMER 0x40 #define APBDEV_PMC_BLINK_TIMER 0x40
#define PMC_BLINK_ON(n) ((n & 0x7FFF)) #define PMC_BLINK_ON(n) ((n & 0x7FFF))
#define PMC_BLINK_FORCE BIT(15) #define PMC_BLINK_FORCE BIT(15)
#define PMC_BLINK_OFF(n) ((u32)(n & 0xFFFF) << 16) #define PMC_BLINK_OFF(n) ((u32)(n & 0xFFFF) << 16)
#define APBDEV_PMC_SCRATCH1 0x54 #define APBDEV_PMC_SCRATCH1 0x54
#define APBDEV_PMC_SCRATCH20 0xA0 #define APBDEV_PMC_SCRATCH20 0xA0 // ODM data/config scratch.
#define APBDEV_PMC_SECURE_SCRATCH4 0xC0 #define APBDEV_PMC_SECURE_SCRATCH4 0xC0
#define APBDEV_PMC_SECURE_SCRATCH5 0xC4 #define APBDEV_PMC_SECURE_SCRATCH5 0xC4
#define APBDEV_PMC_PWR_DET_VAL 0xE4 #define APBDEV_PMC_PWR_DET_VAL 0xE4
@ -68,9 +69,13 @@
#define APBDEV_PMC_CRYPTO_OP 0xF4 #define APBDEV_PMC_CRYPTO_OP 0xF4
#define PMC_CRYPTO_OP_SE_ENABLE 0 #define PMC_CRYPTO_OP_SE_ENABLE 0
#define PMC_CRYPTO_OP_SE_DISABLE 1 #define PMC_CRYPTO_OP_SE_DISABLE 1
#define APBDEV_PMC_PLLP_WB0_OVERRIDE 0xF8
#define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE_ENABLE BIT(11)
#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
#define APBDEV_PMC_SCRATCH33 0x120 #define APBDEV_PMC_SCRATCH33 0x120
#define APBDEV_PMC_SCRATCH37 0x130 #define APBDEV_PMC_SCRATCH37 0x130
#define PMC_SCRATCH37_KERNEL_PANIC_MAGIC 0x4E415054 // "TPAN" #define PMC_SCRATCH37_KERNEL_PANIC_MAGIC 0x4E415054 // "TPAN"
#define APBDEV_PMC_SCRATCH39 0x138
#define APBDEV_PMC_SCRATCH40 0x13C #define APBDEV_PMC_SCRATCH40 0x13C
#define APBDEV_PMC_OSC_EDPD_OVER 0x1A4 #define APBDEV_PMC_OSC_EDPD_OVER 0x1A4
#define PMC_OSC_EDPD_OVER_OSC_CTRL_OVER BIT(22) #define PMC_OSC_EDPD_OVER_OSC_CTRL_OVER BIT(22)
@ -103,14 +108,23 @@
#define APBDEV_PMC_SCRATCH45 0x234 #define APBDEV_PMC_SCRATCH45 0x234
#define APBDEV_PMC_SCRATCH46 0x238 #define APBDEV_PMC_SCRATCH46 0x238
#define APBDEV_PMC_SCRATCH49 0x244 #define APBDEV_PMC_SCRATCH49 0x244
#define APBDEV_PMC_SCRATCH52 0x250
#define APBDEV_PMC_SCRATCH53 0x254
#define APBDEV_PMC_SCRATCH54 0x258
#define APBDEV_PMC_SCRATCH55 0x25C
#define APBDEV_PMC_TSC_MULT 0x2B4 #define APBDEV_PMC_TSC_MULT 0x2B4
#define APBDEV_PMC_STICKY_BITS 0x2C0
#define PMC_STICKY_BITS_HDA_LPBK_DIS BIT(0)
#define APBDEV_PMC_SEC_DISABLE2 0x2C4 #define APBDEV_PMC_SEC_DISABLE2 0x2C4
#define APBDEV_PMC_WEAK_BIAS 0x2C8 #define APBDEV_PMC_WEAK_BIAS 0x2C8
#define APBDEV_PMC_REG_SHORT 0x2CC #define APBDEV_PMC_REG_SHORT 0x2CC
#define APBDEV_PMC_SEC_DISABLE3 0x2D8 #define APBDEV_PMC_SEC_DISABLE3 0x2D8
#define APBDEV_PMC_SECURE_SCRATCH21 0x334 #define APBDEV_PMC_SECURE_SCRATCH21 0x334
#define PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT BIT(4) #define PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT BIT(4)
#define APBDEV_PMC_SECURE_SCRATCH22 0x338 // AArch32 reset address.
#define APBDEV_PMC_SECURE_SCRATCH32 0x360 #define APBDEV_PMC_SECURE_SCRATCH32 0x360
#define APBDEV_PMC_SECURE_SCRATCH34 0x368 // AArch64 reset address.
#define APBDEV_PMC_SECURE_SCRATCH35 0x36C // AArch64 reset hi-address.
#define APBDEV_PMC_SECURE_SCRATCH49 0x3A4 #define APBDEV_PMC_SECURE_SCRATCH49 0x3A4
#define APBDEV_PMC_CNTRL2 0x440 #define APBDEV_PMC_CNTRL2 0x440
#define PMC_CNTRL2_WAKE_INT_EN BIT(0) #define PMC_CNTRL2_WAKE_INT_EN BIT(0)
@ -133,11 +147,25 @@
#define APBDEV_PMC_SCRATCH188 0x810 #define APBDEV_PMC_SCRATCH188 0x810
#define APBDEV_PMC_SCRATCH190 0x818 #define APBDEV_PMC_SCRATCH190 0x818
#define APBDEV_PMC_SCRATCH200 0x840 #define APBDEV_PMC_SCRATCH200 0x840
#define APBDEV_PMC_SCRATCH201 0x844
#define APBDEV_PMC_SCRATCH250 0x908
#define APBDEV_PMC_SECURE_SCRATCH108 0xB08 #define APBDEV_PMC_SECURE_SCRATCH108 0xB08
#define APBDEV_PMC_SECURE_SCRATCH109 0xB0C #define APBDEV_PMC_SECURE_SCRATCH109 0xB0C
#define APBDEV_PMC_SECURE_SCRATCH110 0xB10 #define APBDEV_PMC_SECURE_SCRATCH110 0xB10
#define APBDEV_PMC_SECURE_SCRATCH112 0xB18
#define APBDEV_PMC_SECURE_SCRATCH113 0xB1C
#define APBDEV_PMC_SECURE_SCRATCH119 0xB34
// Only in T210B01. // Only in T210B01.
#define APBDEV_PMC_SCRATCH_WRITE_DISABLE0 0xA48
#define APBDEV_PMC_SCRATCH_WRITE_DISABLE1 0xA4C
#define APBDEV_PMC_SCRATCH_WRITE_DISABLE2 0xA50
#define APBDEV_PMC_SCRATCH_WRITE_DISABLE3 0xA54
#define APBDEV_PMC_SCRATCH_WRITE_DISABLE4 0xA58
#define APBDEV_PMC_SCRATCH_WRITE_DISABLE5 0xA5C
#define APBDEV_PMC_SCRATCH_WRITE_DISABLE6 0xA60
#define APBDEV_PMC_SCRATCH_WRITE_DISABLE7 0xA64
#define APBDEV_PMC_SCRATCH_WRITE_DISABLE8 0xA68
#define APBDEV_PMC_LED_BREATHING_CTRL 0xB48 #define APBDEV_PMC_LED_BREATHING_CTRL 0xB48
#define PMC_LED_BREATHING_CTRL_ENABLE BIT(0) #define PMC_LED_BREATHING_CTRL_ENABLE BIT(0)
#define PMC_LED_BREATHING_CTRL_COUNTER1_EN BIT(1) #define PMC_LED_BREATHING_CTRL_COUNTER1_EN BIT(1)

202
bdk/soc/t210.h
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@ -27,8 +27,10 @@
#define DISPLAY_A_BASE 0x54200000 #define DISPLAY_A_BASE 0x54200000
#define DSI_BASE 0x54300000 #define DSI_BASE 0x54300000
#define VIC_BASE 0x54340000 #define VIC_BASE 0x54340000
#define NVDEC_BASE 0x54480000
#define TSEC_BASE 0x54500000 #define TSEC_BASE 0x54500000
#define SOR1_BASE 0x54580000 #define SOR1_BASE 0x54580000
#define MSELECT_BASE 0x50060000
#define ICTLR_BASE 0x60004000 #define ICTLR_BASE 0x60004000
#define TMR_BASE 0x60005000 #define TMR_BASE 0x60005000
#define CLOCK_BASE 0x60006000 #define CLOCK_BASE 0x60006000
@ -71,6 +73,8 @@
#define I2S_BASE 0x702D1000 #define I2S_BASE 0x702D1000
#define ADMA_BASE 0x702E2000 #define ADMA_BASE 0x702E2000
#define TZRAM_BASE 0x7C010000 #define TZRAM_BASE 0x7C010000
#define TZRAM_SIZE 0x10000
#define TZRAM_T210B01_SIZE 0x3C000
#define USB_BASE 0x7D000000 #define USB_BASE 0x7D000000
#define USB_OTG_BASE USB_BASE #define USB_OTG_BASE USB_BASE
#define USB1_BASE 0x7D004000 #define USB1_BASE 0x7D004000
@ -82,8 +86,10 @@
#define DISPLAY_A(off) _REG(DISPLAY_A_BASE, off) #define DISPLAY_A(off) _REG(DISPLAY_A_BASE, off)
#define DSI(off) _REG(DSI_BASE, off) #define DSI(off) _REG(DSI_BASE, off)
#define VIC(off) _REG(VIC_BASE, off) #define VIC(off) _REG(VIC_BASE, off)
#define NVDEC(off) _REG(NVDEC_BASE, off)
#define TSEC(off) _REG(TSEC_BASE, off) #define TSEC(off) _REG(TSEC_BASE, off)
#define SOR1(off) _REG(SOR1_BASE, off) #define SOR1(off) _REG(SOR1_BASE, off)
#define MSELECT(off) _REG(MSELECT_BASE, off)
#define ICTLR(cidx, off) _REG(ICTLR_BASE + (0x100 * (cidx)), off) #define ICTLR(cidx, off) _REG(ICTLR_BASE + (0x100 * (cidx)), off)
#define TMR(off) _REG(TMR_BASE, off) #define TMR(off) _REG(TMR_BASE, off)
#define CLOCK(off) _REG(CLOCK_BASE, off) #define CLOCK(off) _REG(CLOCK_BASE, off)
@ -130,91 +136,91 @@
#define TEST_REG(off) _REG(0x0, off) #define TEST_REG(off) _REG(0x0, off)
/* HOST1X registers. */ /* HOST1X registers. */
#define HOST1X_CH0_SYNC_BASE 0x2100 #define HOST1X_CH0_SYNC_BASE 0x2100
#define HOST1X_CH0_SYNC_SYNCPT_9 (HOST1X_CH0_SYNC_BASE + 0xFA4) #define HOST1X_CH0_SYNC_SYNCPT_9 (HOST1X_CH0_SYNC_BASE + 0xFA4)
#define HOST1X_CH0_SYNC_SYNCPT_160 (HOST1X_CH0_SYNC_BASE + 0x1200) #define HOST1X_CH0_SYNC_SYNCPT_160 (HOST1X_CH0_SYNC_BASE + 0x1200)
/*! EVP registers. */ /*! EVP registers. */
#define EVP_CPU_RESET_VECTOR 0x100 #define EVP_CPU_RESET_VECTOR 0x100
#define EVP_COP_RESET_VECTOR 0x200 #define EVP_COP_RESET_VECTOR 0x200
#define EVP_COP_UNDEF_VECTOR 0x204 #define EVP_COP_UNDEF_VECTOR 0x204
#define EVP_COP_SWI_VECTOR 0x208 #define EVP_COP_SWI_VECTOR 0x208
#define EVP_COP_PREFETCH_ABORT_VECTOR 0x20C #define EVP_COP_PREFETCH_ABORT_VECTOR 0x20C
#define EVP_COP_DATA_ABORT_VECTOR 0x210 #define EVP_COP_DATA_ABORT_VECTOR 0x210
#define EVP_COP_RSVD_VECTOR 0x214 #define EVP_COP_RSVD_VECTOR 0x214
#define EVP_COP_IRQ_VECTOR 0x218 #define EVP_COP_IRQ_VECTOR 0x218
#define EVP_COP_FIQ_VECTOR 0x21C #define EVP_COP_FIQ_VECTOR 0x21C
#define EVP_COP_IRQ_STS 0x220 #define EVP_COP_IRQ_STS 0x220
/*! Primary Interrupt Controller registers. */ /*! Primary Interrupt Controller registers. */
#define PRI_ICTLR_FIR 0x14 #define PRI_ICTLR_FIR 0x14
#define PRI_ICTLR_FIR_SET 0x18 #define PRI_ICTLR_FIR_SET 0x18
#define PRI_ICTLR_FIR_CLR 0x1C #define PRI_ICTLR_FIR_CLR 0x1C
#define PRI_ICTLR_CPU_IER 0x20 #define PRI_ICTLR_CPU_IER 0x20
#define PRI_ICTLR_CPU_IER_SET 0x24 #define PRI_ICTLR_CPU_IER_SET 0x24
#define PRI_ICTLR_CPU_IER_CLR 0x28 #define PRI_ICTLR_CPU_IER_CLR 0x28
#define PRI_ICTLR_CPU_IEP_CLASS 0x2C #define PRI_ICTLR_CPU_IEP_CLASS 0x2C
#define PRI_ICTLR_COP_IER 0x30 #define PRI_ICTLR_COP_IER 0x30
#define PRI_ICTLR_COP_IER_SET 0x34 #define PRI_ICTLR_COP_IER_SET 0x34
#define PRI_ICTLR_COP_IER_CLR 0x38 #define PRI_ICTLR_COP_IER_CLR 0x38
#define PRI_ICTLR_COP_IEP_CLASS 0x3C #define PRI_ICTLR_COP_IEP_CLASS 0x3C
/*! AHB Gizmo registers. */ /*! AHB Gizmo registers. */
#define AHB_ARBITRATION_PRIORITY_CTRL 0x8 #define AHB_ARBITRATION_PRIORITY_CTRL 0x8
#define PRIORITY_CTRL_WEIGHT(x) (((x) & 7) << 29) #define PRIORITY_CTRL_WEIGHT(x) (((x) & 7) << 29)
#define PRIORITY_SELECT_USB BIT(6) // USB-OTG. #define PRIORITY_SELECT_USB BIT(6) // USB-OTG.
#define PRIORITY_SELECT_USB2 BIT(18) // USB-HSIC. #define PRIORITY_SELECT_USB2 BIT(18) // USB-HSIC.
#define PRIORITY_SELECT_USB3 BIT(17) // XUSB. #define PRIORITY_SELECT_USB3 BIT(17) // XUSB.
#define AHB_GIZMO_AHB_MEM 0x10 #define AHB_GIZMO_AHB_MEM 0x10
#define AHB_MEM_ENB_FAST_REARBITRATE BIT(2) #define AHB_MEM_ENB_FAST_REARBITRATE BIT(2)
#define AHB_MEM_DONT_SPLIT_AHB_WR BIT(7) #define AHB_MEM_DONT_SPLIT_AHB_WR BIT(7)
#define AHB_MEM_IMMEDIATE BIT(18) #define AHB_MEM_IMMEDIATE BIT(18)
#define AHB_GIZMO_APB_DMA 0x14 #define AHB_GIZMO_APB_DMA 0x14
#define AHB_GIZMO_USB 0x20 #define AHB_GIZMO_USB 0x20
#define AHB_GIZMO_SDMMC4 0x48 #define AHB_GIZMO_SDMMC4 0x48
#define AHB_GIZMO_USB2 0x7C #define AHB_GIZMO_USB2 0x7C
#define AHB_GIZMO_USB3 0x80 #define AHB_GIZMO_USB3 0x80
#define AHB_GIZMO_IMMEDIATE BIT(18) #define AHB_GIZMO_IMMEDIATE BIT(18)
#define AHB_ARBITRATION_XBAR_CTRL 0xE0 #define AHB_ARBITRATION_XBAR_CTRL 0xE0
#define AHB_AHB_MEM_PREFETCH_CFG3 0xE4 #define AHB_AHB_MEM_PREFETCH_CFG3 0xE4
#define AHB_AHB_MEM_PREFETCH_CFG4 0xE8 #define AHB_AHB_MEM_PREFETCH_CFG4 0xE8
#define AHB_AHB_MEM_PREFETCH_CFG1 0xF0 #define AHB_AHB_MEM_PREFETCH_CFG1 0xF0
#define AHB_AHB_MEM_PREFETCH_CFG2 0xF4 #define AHB_AHB_MEM_PREFETCH_CFG2 0xF4
#define MST_ID(x) (((x) & 0x1F) << 26) #define MST_ID(x) (((x) & 0x1F) << 26)
#define MEM_PREFETCH_AHBDMA_MST_ID MST_ID(5) #define MEM_PREFETCH_AHBDMA_MST_ID MST_ID(5)
#define MEM_PREFETCH_USB_MST_ID MST_ID(6) // USB-OTG. #define MEM_PREFETCH_USB_MST_ID MST_ID(6) // USB-OTG.
#define MEM_PREFETCH_USB2_MST_ID MST_ID(18) // USB-HSIC. #define MEM_PREFETCH_USB2_MST_ID MST_ID(18) // USB-HSIC.
#define MEM_PREFETCH_USB3_MST_ID MST_ID(17) // XUSB. #define MEM_PREFETCH_USB3_MST_ID MST_ID(17) // XUSB.
#define MEM_PREFETCH_ADDR_BNDRY(x) (((x) & 0xF) << 21) #define MEM_PREFETCH_ADDR_BNDRY(x) (((x) & 0xF) << 21)
#define MEM_PREFETCH_ENABLE BIT(31) #define MEM_PREFETCH_ENABLE BIT(31)
#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID 0xFC #define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID 0xFC
#define MEM_WRQUE_SE_MST_ID BIT(14) #define MEM_WRQUE_SE_MST_ID BIT(14)
#define AHB_AHB_SPARE_REG 0x110 #define AHB_AHB_SPARE_REG 0x110
/*! Misc registers. */ /*! Misc registers. */
#define APB_MISC_PP_STRAPPING_OPT_A 0x08 #define APB_MISC_PP_STRAPPING_OPT_A 0x8
#define APB_MISC_PP_PINMUX_GLOBAL 0x40 #define APB_MISC_PP_PINMUX_GLOBAL 0x40
#define APB_MISC_GP_HIDREV 0x804 #define APB_MISC_GP_HIDREV 0x804
#define GP_HIDREV_MAJOR_T210 0x1 #define GP_HIDREV_MAJOR_T210 0x1
#define GP_HIDREV_MAJOR_T210B01 0x2 #define GP_HIDREV_MAJOR_T210B01 0x2
#define APB_MISC_GP_ASDBGREG 0x810 #define APB_MISC_GP_ASDBGREG 0x810
#define APB_MISC_GP_AUD_MCLK_CFGPADCTRL 0x8F4 #define APB_MISC_GP_AUD_MCLK_CFGPADCTRL 0x8F4
#define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34 #define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL 0xA98 #define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL 0xA98
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL 0xA9C #define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL 0xA9C
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL 0xAB4 #define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL 0xAB4
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL 0xABC #define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL 0xABC
#define APB_MISC_GP_DSI_PAD_CONTROL 0xAC0 #define APB_MISC_GP_DSI_PAD_CONTROL 0xAC0
#define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64 #define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64
#define APB_MISC_GP_WIFI_RST_CFGPADCTRL 0xB68 #define APB_MISC_GP_WIFI_RST_CFGPADCTRL 0xB68
/*! Secure boot registers. */ /*! Secure boot registers. */
#define SB_CSR 0x0 #define SB_CSR 0x0
#define SB_CSR_NS_RST_VEC_WR_DIS BIT(1) #define SB_CSR_NS_RST_VEC_WR_DIS BIT(1)
#define SB_CSR_PIROM_DISABLE BIT(4) #define SB_CSR_PIROM_DISABLE BIT(4)
#define SB_AA64_RESET_LOW 0x30 #define SB_AA64_RESET_LOW 0x30
#define SB_AA64_RST_AARCH64_MODE_EN BIT(0) #define SB_AA64_RST_AARCH64_MODE_EN BIT(0)
#define SB_AA64_RESET_HIGH 0x34 #define SB_AA64_RESET_HIGH 0x34
/*! SOR registers. */ /*! SOR registers. */
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB 0x1E8 #define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB 0x1E8
@ -231,7 +237,7 @@
#define SYSCTR0_CNTCR 0x00 #define SYSCTR0_CNTCR 0x00
#define SYSCTR0_CNTFID0 0x20 #define SYSCTR0_CNTFID0 0x20
#define SYSCTR0_COUNTERS_BASE 0xFD0 #define SYSCTR0_COUNTERS_BASE 0xFD0
#define SYSCTR0_COUNTERS 12 #define SYSCTR0_COUNTERS 12
#define SYSCTR0_COUNTERID0 0xFE0 #define SYSCTR0_COUNTERID0 0xFE0
#define SYSCTR0_COUNTERID1 0xFE4 #define SYSCTR0_COUNTERID1 0xFE4
#define SYSCTR0_COUNTERID2 0xFE8 #define SYSCTR0_COUNTERID2 0xFE8
@ -269,28 +275,42 @@
#define EMC_HEKA_UPD BIT(30) #define EMC_HEKA_UPD BIT(30)
/*! Flow controller registers. */ /*! Flow controller registers. */
#define FLOW_CTLR_HALT_COP_EVENTS 0x4 #define FLOW_CTLR_HALT_COP_EVENTS 0x4
#define HALT_COP_GIC_IRQ BIT(9) #define HALT_COP_GIC_IRQ BIT(9)
#define HALT_COP_LIC_IRQ BIT(11) #define HALT_COP_LIC_IRQ BIT(11)
#define HALT_COP_SEC BIT(23) #define HALT_COP_SEC BIT(23)
#define HALT_COP_MSEC BIT(24) #define HALT_COP_MSEC BIT(24)
#define HALT_COP_USEC BIT(25) #define HALT_COP_USEC BIT(25)
#define HALT_COP_JTAG BIT(28) #define HALT_COP_JTAG BIT(28)
#define HALT_COP_WAIT_EVENT BIT(30) #define HALT_COP_WAIT_EVENT BIT(30)
#define HALT_COP_STOP_UNTIL_IRQ BIT(31) #define HALT_COP_STOP_UNTIL_IRQ BIT(31)
#define HALT_COP_MAX_CNT 0xFF #define HALT_COP_MAX_CNT 0xFF
#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0 #define FLOW_CTLR_HALT_CPU0_EVENTS 0x0
#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14 #define FLOW_CTLR_HALT_CPU1_EVENTS 0x14
#define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C #define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C
#define FLOW_CTLR_HALT_CPU3_EVENTS 0x24 #define FLOW_CTLR_HALT_CPU3_EVENTS 0x24
#define FLOW_CTLR_CPU0_CSR 0x8 #define FLOW_CTLR_CPU0_CSR 0x8
#define FLOW_CTLR_CPU1_CSR 0x18 #define FLOW_CTLR_CPU1_CSR 0x18
#define FLOW_CTLR_CPU2_CSR 0x20 #define FLOW_CTLR_CPU2_CSR 0x20
#define FLOW_CTLR_CPU3_CSR 0x28 #define FLOW_CTLR_CPU3_CSR 0x28
#define FLOW_CTLR_RAM_REPAIR 0x40 #define FLOW_CTLR_RAM_REPAIR 0x40
#define RAM_REPAIR_REQ BIT(0) #define RAM_REPAIR_REQ BIT(0)
#define RAM_REPAIR_STS BIT(1) #define RAM_REPAIR_STS BIT(1)
#define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98 #define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98
#define CLUSTER_CTRL_ACTIVE_SLOW BIT(0) #define CLUSTER_CTRL_ACTIVE_SLOW BIT(0)
/* MSelect registers */
#define MSELECT_CONFIG 0x00
#define MSELECT_CFG_ERR_RESP_EN_PCIE BIT(24)
#define MSELECT_CFG_ERR_RESP_EN_GPU BIT(25)
#define MSELECT_CFG_WRAP_TO_INCR_BPMP BIT(27)
#define MSELECT_CFG_WRAP_TO_INCR_PCIE BIT(28)
#define MSELECT_CFG_WRAP_TO_INCR_GPU BIT(29)
/* NVDEC registers */
#define NVDEC_SA_KEYSLOT_FALCON 0x2100
#define NVDEC_SA_KEYSLOT_TZ 0x2104
#define NVDEC_SA_KEYSLOT_OTF 0x210C
#define NVDEC_SA_KEYSLOT_GLOBAL_RW 0x2118
#define NVDEC_VPR_ALL_OTF_GOTO_VPR 0x211C
#endif #endif