forked from CTCaer/hekate
bdk: smmu: refactor and update driver
- Allow ASID to be configured - Allow 34-bit PAs - Use special type for setting PDE/PTE config - Initialize all pages as non accessible - Add function for mapping 4MB regions directly - Add SMMU heap reset function - Correct address load OP to 32-bit and remove alignment on SMMU enable payload - Refactor all defines
This commit is contained in:
CTCaer
parent
0100c11757
commit
9e41aa7759
213
bdk/mem/smmu.c
213
bdk/mem/smmu.c
@ -18,6 +18,7 @@
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#include <string.h>
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#include <soc/bpmp.h>
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#include <soc/ccplex.h>
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#include <soc/timer.h>
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#include <soc/t210.h>
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@ -25,27 +26,39 @@
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#include <mem/smmu.h>
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#include <memory_map.h>
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#define SMMU_PAGE_SHIFT 12
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#define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT)
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/*! SMMU register defines */
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#define SMMU_ASID(asid) (((asid) << 24u) | ((asid) << 16u) | ((asid) << 8u) | (asid))
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#define SMMU_ENABLE BIT(31)
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#define SMMU_TLB_ACTIVE_LINES(l) ((l) << 0u)
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#define SMMU_TLB_RR_ARBITRATION BIT(28)
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#define SMMU_TLB_HIT_UNDER_MISS BIT(29)
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#define SMMU_TLB_STATS_ENABLE BIT(31)
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#define SMUU_PTC_INDEX_MAP(m) ((m) << 0u)
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#define SMUU_PTC_LINE_MASK(m) ((m) << 8u)
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#define SMUU_PTC_REQ_LIMIT(l) ((l) << 24u)
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#define SMUU_PTC_CACHE_ENABLE BIT(29)
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#define SMUU_PTC_STATS_ENABLE BIT(31)
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/*! Page table defines */
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#define SMMU_4MB_REGION 0
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#define SMMU_PAGE_TABLE 1
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#define SMMU_PDIR_COUNT 1024
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#define SMMU_PDIR_SIZE (sizeof(u32) * SMMU_PDIR_COUNT)
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#define SMMU_PTBL_COUNT 1024
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#define SMMU_PTBL_SIZE (sizeof(u32) * SMMU_PTBL_COUNT)
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#define SMMU_PDIR_SHIFT 12
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#define SMMU_PDE_SHIFT 12
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#define SMMU_PTE_SHIFT 12
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#define SMMU_PFN_MASK 0x000FFFFF
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#define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12)
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#define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22)
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#define SMMU_PDN_TO_ADDR(addr) ((pdn) << 22)
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#define SMMU_MK_PDIR(page, attr) (((page) >> SMMU_PDIR_SHIFT) | (attr))
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#define SMMU_MK_PDE(page, attr) (((page) >> SMMU_PDE_SHIFT) | (attr))
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#define SMMU_PAGE_SHIFT 12u
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#define SMMU_PTN_SHIFT SMMU_PAGE_SHIFT
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#define SMMU_PDN_SHIFT 22u
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#define SMMU_ADDR_TO_PFN(addr) ((addr) >> SMMU_PAGE_SHIFT)
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#define SMMU_ADDR_TO_PTN(addr) ((addr) >> SMMU_PTN_SHIFT)
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#define SMMU_ADDR_TO_PDN(addr) ((addr) >> SMMU_PDN_SHIFT)
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#define SMMU_PTN_TO_ADDR(ptn) ((ptn) << SMMU_PTN_SHIFT)
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#define SMMU_PDN_TO_ADDR(pdn) ((pdn) << SMMU_PDN_SHIFT)
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#define SMMU_PTB(page, attr) (((attr) << 29u) | ((page) >> SMMU_PAGE_SHIFT))
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u8 *_pageheap = (u8 *)SMMU_HEAP_ADDR;
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static void *smmu_heap = (void *)SMMU_HEAP_ADDR;
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// Enabling SMMU requires a TZ secure write: MC(MC_SMMU_CONFIG) = 1;
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u8 smmu_payload[] __attribute__((aligned(16))) = {
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0xC1, 0x00, 0x00, 0x58, // 0x00: LDR X1, =0x70019010
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// Enabling SMMU requires a TZ (EL3) secure write. MC(MC_SMMU_CONFIG) = 1;
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static const u8 smmu_enable_payload[] = {
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0xC1, 0x00, 0x00, 0x18, // 0x00: LDR W1, =0x70019010
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0x20, 0x00, 0x80, 0xD2, // 0x04: MOV X0, #0x1
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0x20, 0x00, 0x00, 0xB9, // 0x08: STR W0, [X1]
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0x1F, 0x71, 0x08, 0xD5, // 0x0C: IC IALLUIS
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@ -56,17 +69,22 @@ u8 smmu_payload[] __attribute__((aligned(16))) = {
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void *smmu_page_zalloc(u32 num)
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{
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u8 *res = _pageheap;
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_pageheap += SZ_PAGE * num;
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memset(res, 0, SZ_PAGE * num);
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return res;
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void *page = smmu_heap;
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memset(page, 0, SZ_PAGE * num);
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smmu_heap += SZ_PAGE * num;
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return page;
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}
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static u32 *_smmu_pdir_alloc()
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static pde_t *_smmu_pdir_alloc()
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{
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u32 *pdir = (u32 *)smmu_page_zalloc(1);
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for (int pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
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pdir[pdn] = _PDE_VACANT(pdn);
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pde_t *pdir = (pde_t *)smmu_page_zalloc(1);
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// Initialize pdes with no permissions.
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for (u32 pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
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pdir[pdn].huge.page = pdn;
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return pdir;
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}
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@ -77,9 +95,12 @@ static void _smmu_flush_regs()
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void smmu_flush_all()
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{
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// Flush the entire page table cache.
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MC(MC_SMMU_PTC_FLUSH) = 0;
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_smmu_flush_regs();
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// Flush the entire table.
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MC(MC_SMMU_TLB_FLUSH) = 0;
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_smmu_flush_regs();
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}
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@ -88,8 +109,8 @@ void smmu_init()
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{
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MC(MC_SMMU_PTB_ASID) = 0;
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MC(MC_SMMU_PTB_DATA) = 0;
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MC(MC_SMMU_TLB_CONFIG) = 0x30000030;
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MC(MC_SMMU_PTC_CONFIG) = 0x28000F3F;
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MC(MC_SMMU_TLB_CONFIG) = SMMU_TLB_HIT_UNDER_MISS | SMMU_TLB_RR_ARBITRATION | SMMU_TLB_ACTIVE_LINES(48);
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MC(MC_SMMU_PTC_CONFIG) = SMUU_PTC_CACHE_ENABLE | SMUU_PTC_REQ_LIMIT(8) | SMUU_PTC_LINE_MASK(0xF) | SMUU_PTC_INDEX_MAP(0x3F);
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MC(MC_SMMU_PTC_FLUSH) = 0;
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MC(MC_SMMU_TLB_FLUSH) = 0;
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}
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@ -101,7 +122,8 @@ void smmu_enable()
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if (enabled)
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return;
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ccplex_boot_cpu0((u32)smmu_payload, false);
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// Launch payload on CCPLEX in order to set SMMU enable bit.
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ccplex_boot_cpu0((u32)smmu_enable_payload, false);
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msleep(100);
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ccplex_powergate_cpu0();
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@ -110,63 +132,114 @@ void smmu_enable()
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enabled = true;
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}
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u32 *smmu_init_domain4(u32 dev_base, u32 asid)
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void smmu_reset_heap()
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{
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u32 *pdir = _smmu_pdir_alloc();
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smmu_heap = (void *)SMMU_HEAP_ADDR;
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}
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void *smmu_init_domain(u32 dev_base, u32 asid)
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{
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void *ptb = _smmu_pdir_alloc();
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MC(MC_SMMU_PTB_ASID) = asid;
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MC(MC_SMMU_PTB_DATA) = SMMU_MK_PDIR((u32)pdir, _PDIR_ATTR);
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MC(MC_SMMU_PTB_DATA) = SMMU_PTB((u32)ptb, SMMU_ATTR_ALL);
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_smmu_flush_regs();
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MC(dev_base) = 0x80000000 | (asid << 24) | (asid << 16) | (asid << 8) | (asid);
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// Use the same macro for both quad and single domains. Reserved bits are not set anyway.
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MC(dev_base) = SMMU_ENABLE | SMMU_ASID(asid);
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_smmu_flush_regs();
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return pdir;
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return ptb;
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}
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u32 *smmu_get_pte(u32 *pdir, u32 iova)
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void smmu_deinit_domain(u32 dev_base, u32 asid)
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{
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u32 ptn = SMMU_ADDR_TO_PFN(iova);
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u32 pdn = SMMU_ADDR_TO_PDN(iova);
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u32 *ptbl;
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MC(MC_SMMU_PTB_ASID) = asid;
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MC(MC_SMMU_PTB_DATA) = 0;
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MC(dev_base) = 0;
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_smmu_flush_regs();
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}
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if (pdir[pdn] != _PDE_VACANT(pdn))
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ptbl = (u32 *)((pdir[pdn] & SMMU_PFN_MASK) << SMMU_PDIR_SHIFT);
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void smmu_domain_bypass(u32 dev_base, bool bypass)
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{
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if (bypass)
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{
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smmu_flush_all();
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false);
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MC(dev_base) &= ~SMMU_ENABLE;
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}
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else
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{
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ptbl = (u32 *)smmu_page_zalloc(1);
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u32 addr = SMMU_PDN_TO_ADDR(pdn);
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for (int pn = 0; pn < SMMU_PTBL_COUNT; pn++, addr += SMMU_PAGE_SIZE)
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ptbl[pn] = _PTE_VACANT(addr);
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pdir[pdn] = SMMU_MK_PDE((u32)ptbl, _PDE_ATTR | _PDE_NEXT);
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false);
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MC(dev_base) |= SMMU_ENABLE;
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smmu_flush_all();
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}
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return &ptbl[ptn % SMMU_PTBL_COUNT];
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}
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void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr)
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{
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for (int i = 0; i < cnt; i++)
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{
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u32 *pte = smmu_get_pte(pdir, addr);
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*pte = SMMU_ADDR_TO_PFN(page) | attr;
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addr += SZ_PAGE;
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page += SZ_PAGE;
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}
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smmu_flush_all();
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}
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u32 *smmu_init_domain(u32 asid)
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{
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return smmu_init_domain4(asid, 1);
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}
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void smmu_deinit_domain(u32 asid)
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{
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MC(MC_SMMU_PTB_ASID) = 1;
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MC(MC_SMMU_PTB_DATA) = 0;
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MC(asid) = 0;
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_smmu_flush_regs();
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}
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static pte_t *_smmu_get_pte(pde_t *pdir, u32 iova)
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{
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u32 pdn = SMMU_ADDR_TO_PDN(iova);
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pte_t *ptbl;
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// Get 4MB page table or initialize one.
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if (pdir[pdn].tbl.attr)
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ptbl = (pte_t *)(SMMU_PTN_TO_ADDR(pdir[pdn].tbl.table));
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else
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{
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// Allocate page table.
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ptbl = (pte_t *)smmu_page_zalloc(1);
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// Get address.
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u32 addr = SMMU_PDN_TO_ADDR(pdn);
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// Initialize page table with no permissions.
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for (u32 pn = 0; pn < SMMU_PTBL_COUNT; pn++, addr += SZ_PAGE)
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ptbl[pn].page = SMMU_ADDR_TO_PFN(addr);
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// Set page table to the page directory.
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pdir[pdn].tbl.table = SMMU_ADDR_TO_PTN((u32)ptbl);
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pdir[pdn].tbl.next = SMMU_PAGE_TABLE;
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pdir[pdn].tbl.attr = SMMU_ATTR_ALL;
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smmu_flush_all();
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}
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return &ptbl[SMMU_ADDR_TO_PTN(iova) % SMMU_PTBL_COUNT];
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}
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void smmu_map(void *ptb, u32 iova, u64 iopa, u32 pages, u32 attr)
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{
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// Map pages to page table entries. VA/PA should be aligned to 4KB.
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for (u32 i = 0; i < pages; i++)
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{
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pte_t *pte = _smmu_get_pte((pde_t *)ptb, iova);
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pte->page = SMMU_ADDR_TO_PFN(iopa);
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pte->attr = attr;
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iova += SZ_PAGE;
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iopa += SZ_PAGE;
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}
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smmu_flush_all();
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}
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void smmu_map_huge(void *ptb, u32 iova, u64 iopa, u32 regions, u32 attr)
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{
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pde_t *pdir = (pde_t *)ptb;
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// Map 4MB regions to page directory entries. VA/PA should be aligned to 4MB.
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for (u32 i = 0; i < regions; i++)
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{
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u32 pdn = SMMU_ADDR_TO_PDN(iova);
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pdir[pdn].huge.page = SMMU_ADDR_TO_PDN(iopa);
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pdir[pdn].huge.next = SMMU_4MB_REGION;
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pdir[pdn].huge.attr = attr;
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iova += SZ_4M;
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iopa += SZ_4M;
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}
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smmu_flush_all();
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}
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@ -15,32 +15,57 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <assert.h>
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#include <utils/types.h>
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#define MC_SMMU_AVPC_ASID 0x23C
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#define MC_SMMU_TSEC_ASID 0x294
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#define SMMU_PDE_NEXT_SHIFT 28
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#define MC_SMMU_PTB_DATA_0_ASID_NONSECURE_SHIFT 29
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#define MC_SMMU_PTB_DATA_0_ASID_WRITABLE_SHIFT 30
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#define MC_SMMU_PTB_DATA_0_ASID_READABLE_SHIFT 31
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#define _READABLE (1 << MC_SMMU_PTB_DATA_0_ASID_READABLE_SHIFT)
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#define _WRITABLE (1 << MC_SMMU_PTB_DATA_0_ASID_WRITABLE_SHIFT)
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#define _NONSECURE (1 << MC_SMMU_PTB_DATA_0_ASID_NONSECURE_SHIFT)
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#define _PDE_NEXT (1 << SMMU_PDE_NEXT_SHIFT)
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#define _MASK_ATTR (_READABLE | _WRITABLE | _NONSECURE)
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#define _PDIR_ATTR (_READABLE | _WRITABLE | _NONSECURE)
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#define _PDE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
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#define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR)
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#define _PTE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
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#define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
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#define SMMU_NS BIT(0)
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#define SMMU_WRITE BIT(1)
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#define SMMU_READ BIT(2)
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#define SMMU_ATTR_ALL (SMMU_READ | SMMU_WRITE | SMMU_NS)
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typedef struct _pde_t {
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union {
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union {
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struct {
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u32 table:22;
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u32 rsvd:6;
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u32 next:1;
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u32 attr:3;
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} tbl;
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struct {
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u32 rsvd_:10;
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u32 page:12;
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u32 rsvd:6;
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u32 next:1;
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u32 attr:3;
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} huge;
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};
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u32 pde;
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};
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} pde_t;
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typedef struct _pte_t {
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u32 page:22;
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u32 rsvd:7;
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u32 attr:3;
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} pte_t;
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static_assert(sizeof(pde_t) == sizeof(u32), "pde_t size is wrong!");
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static_assert(sizeof(pte_t) == sizeof(u32), "pte_t size is wrong!");
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void *smmu_page_zalloc(u32 num);
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void smmu_flush_all();
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void smmu_init();
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void smmu_enable();
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u32 *smmu_init_domain4(u32 dev_base, u32 asid);
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u32 *smmu_get_pte(u32 *pdir, u32 iova);
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void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr);
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u32 *smmu_init_domain(u32 asid);
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void smmu_deinit_domain(u32 asid);
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void smmu_reset_heap();
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void *smmu_init_domain(u32 dev_base, u32 asid);
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void smmu_deinit_domain(u32 dev_base, u32 asid);
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void smmu_domain_bypass(u32 dev_base, bool bypass);
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void smmu_map(void *ptb, u32 iova, u64 iopa, u32 pages, u32 attr);
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void smmu_map_huge(void *ptb, u32 iova, u64 iopa, u32 regions, u32 attr);
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@ -70,8 +70,9 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
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int res = 0;
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u8 *fwbuf = NULL;
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u32 type = tsec_ctxt->type;
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u32 *pdir, *car, *fuse, *pmc, *flowctrl, *se, *mc, *iram, *evec;
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u32 *car, *fuse, *pmc, *flowctrl, *se, *mc, *iram, *evec;
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u32 *pkg11_magic_off;
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void *ptb;
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bpmp_mmu_disable();
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bpmp_freq_t prev_fid = bpmp_clk_rate_set(BPMP_CLK_NORMAL);
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@ -145,7 +146,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
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if (type == TSEC_FW_TYPE_EMU)
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{
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// Init SMMU translation for TSEC.
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pdir = smmu_init_domain(MC_SMMU_TSEC_ASID);
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ptb = smmu_init_domain(MC_SMMU_TSEC_ASID, 1);
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smmu_init();
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// Enable SMMU.
|
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@ -155,7 +156,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
|
||||
car = smmu_page_zalloc(1);
|
||||
memcpy(car, (void *)CLOCK_BASE, SZ_PAGE);
|
||||
car[CLK_RST_CONTROLLER_CLK_SOURCE_TSEC / 4] = CLK_SRC_DIV(2);
|
||||
smmu_map(pdir, CLOCK_BASE, (u32)car, 1, _WRITABLE | _READABLE | _NONSECURE);
|
||||
smmu_map(ptb, CLOCK_BASE, (u32)car, 1, SMMU_WRITE | SMMU_READ | SMMU_NS);
|
||||
|
||||
// Fuse driver.
|
||||
fuse = smmu_page_zalloc(1);
|
||||
@ -163,38 +164,38 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
|
||||
fuse[0x82C / 4] = 0;
|
||||
fuse[0x9E0 / 4] = (1 << (TSEC_HOS_KB_620 + 2)) - 1;
|
||||
fuse[0x9E4 / 4] = (1 << (TSEC_HOS_KB_620 + 2)) - 1;
|
||||
smmu_map(pdir, (FUSE_BASE - 0x800), (u32)fuse, 1, _READABLE | _NONSECURE);
|
||||
smmu_map(ptb, (FUSE_BASE - 0x800), (u32)fuse, 1, SMMU_READ | SMMU_NS);
|
||||
|
||||
// Power management controller.
|
||||
pmc = smmu_page_zalloc(1);
|
||||
smmu_map(pdir, RTC_BASE, (u32)pmc, 1, _READABLE | _NONSECURE);
|
||||
smmu_map(ptb, RTC_BASE, (u32)pmc, 1, SMMU_READ | SMMU_NS);
|
||||
|
||||
// Flow control.
|
||||
flowctrl = smmu_page_zalloc(1);
|
||||
smmu_map(pdir, FLOW_CTLR_BASE, (u32)flowctrl, 1, _WRITABLE | _NONSECURE);
|
||||
smmu_map(ptb, FLOW_CTLR_BASE, (u32)flowctrl, 1, SMMU_WRITE | SMMU_NS);
|
||||
|
||||
// Security engine.
|
||||
se = smmu_page_zalloc(1);
|
||||
memcpy(se, (void *)SE_BASE, SZ_PAGE);
|
||||
smmu_map(pdir, SE_BASE, (u32)se, 1, _READABLE | _WRITABLE | _NONSECURE);
|
||||
smmu_map(ptb, SE_BASE, (u32)se, 1, SMMU_READ | SMMU_WRITE | SMMU_NS);
|
||||
|
||||
// Memory controller.
|
||||
mc = smmu_page_zalloc(1);
|
||||
memcpy(mc, (void *)MC_BASE, SZ_PAGE);
|
||||
mc[MC_IRAM_BOM / 4] = 0;
|
||||
mc[MC_IRAM_TOM / 4] = DRAM_START;
|
||||
smmu_map(pdir, MC_BASE, (u32)mc, 1, _READABLE | _NONSECURE);
|
||||
smmu_map(ptb, MC_BASE, (u32)mc, 1, SMMU_READ | SMMU_NS);
|
||||
|
||||
// IRAM
|
||||
iram = smmu_page_zalloc(0x30);
|
||||
memcpy(iram, tsec_ctxt->pkg1, 0x30000);
|
||||
// PKG1.1 magic offset.
|
||||
pkg11_magic_off = (u32 *)(iram + ((tsec_ctxt->pkg11_off + 0x20) / 4));
|
||||
smmu_map(pdir, 0x40010000, (u32)iram, 0x30, _READABLE | _WRITABLE | _NONSECURE);
|
||||
pkg11_magic_off = (u32 *)(iram + ((tsec_ctxt->pkg11_off + 0x20) / sizeof(u32)));
|
||||
smmu_map(ptb, 0x40010000, (u32)iram, 0x30, SMMU_READ | SMMU_WRITE | SMMU_NS);
|
||||
|
||||
// Exception vectors
|
||||
evec = smmu_page_zalloc(1);
|
||||
smmu_map(pdir, EXCP_VEC_BASE, (u32)evec, 1, _READABLE | _WRITABLE | _NONSECURE);
|
||||
smmu_map(ptb, EXCP_VEC_BASE, (u32)evec, 1, SMMU_READ | SMMU_WRITE | SMMU_NS);
|
||||
}
|
||||
|
||||
// Execute firmware.
|
||||
@ -229,7 +230,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
|
||||
if (kidx != 8)
|
||||
{
|
||||
res = -6;
|
||||
smmu_deinit_domain(MC_SMMU_TSEC_ASID);
|
||||
smmu_deinit_domain(MC_SMMU_TSEC_ASID, 1);
|
||||
|
||||
goto out_free;
|
||||
}
|
||||
@ -240,7 +241,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
|
||||
memcpy(tsec_keys, &key, 0x20);
|
||||
memcpy(tsec_ctxt->pkg1, iram, 0x30000);
|
||||
|
||||
smmu_deinit_domain(MC_SMMU_TSEC_ASID);
|
||||
smmu_deinit_domain(MC_SMMU_TSEC_ASID, 1);
|
||||
|
||||
// for (int i = 0; i < kidx; i++)
|
||||
// gfx_printf("key %08X\n", key[i]);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user