forked from CTCaer/hekate
l4t: bump loader/firmware revisions
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@ -33,9 +33,12 @@
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* 1: SDMMC1 LA programming for SDMMC1 UHS DDR200.
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* 1: SDMMC1 LA programming for SDMMC1 UHS DDR200.
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* 2: Arachne Register Cell v1.
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* 2: Arachne Register Cell v1.
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* 3: Arachne Register Cell v2. PTSA Rework support.
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* 3: Arachne Register Cell v2. PTSA Rework support.
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* 4: Arachne Register Cell v3. DRAM OPT and DDR200 changes.
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* 5: Arachne Register Cell v4. DRAM FREQ and DDR200 changes.
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*/
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*/
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#define L4T_LOADER_API_REV 4
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#define L4T_FIRMWARE_REV 0x34524556 // REV4.
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#define L4T_LOADER_API_REV 5
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#define L4T_FIRMWARE_REV 0x35524556 // REV5.
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#ifdef DEBUG_UART_PORT
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#ifdef DEBUG_UART_PORT
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#include <soc/uart.h>
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#include <soc/uart.h>
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