forked from CTCaer/hekate
bdk: add missed defines
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5453c593a3
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@ -40,7 +40,7 @@
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#define GPU_USER_BASE 0x58000000
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#define RES_SEMAPH_BASE 0x60001000
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#define ARB_SEMAPH_BASE 0x60002000
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#define ARBPRI_BASE 0x60003000
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#define ARB_PRI_BASE 0x60003000
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#define ICTLR_BASE 0x60004000
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#define TMR_BASE 0x60005000
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#define CLOCK_BASE 0x60006000
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@ -112,6 +112,7 @@
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#define SOR1(off) MMIO_REG32(SOR1_BASE, off)
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#define GPU(off) MMIO_REG32(GPU_BASE, off)
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#define GPU_USER(off) MMIO_REG32(GPU_USER_BASE, off)
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#define ARB_PRI(off) MMIO_REG32(ARB_PRI_BASE, off)
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#define ICTLR(cidx, off) MMIO_REG32(ICTLR_BASE + (0x100 * (cidx)), off)
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#define TMR(off) MMIO_REG32(TMR_BASE, off)
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#define CLOCK(off) MMIO_REG32(CLOCK_BASE, off)
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@ -174,6 +175,7 @@
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#define EVP_COP_IRQ_STS 0x220
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/*! Primary Interrupt Controller registers. */
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#define PRI_ICTLR_ISR 0x10
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#define PRI_ICTLR_FIR 0x14
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#define PRI_ICTLR_FIR_SET 0x18
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#define PRI_ICTLR_FIR_CLR 0x1C
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@ -186,6 +188,13 @@
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#define PRI_ICTLR_COP_IER_CLR 0x38
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#define PRI_ICTLR_COP_IEP_CLASS 0x3C
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/* Arbiter registers */
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#define ARB_PRIO_CPU_PRIORITY 0x0
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#define ARB_PRIO_COP_PRIORITY 0x4
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#define ARB_PRIO_VCP_PRIORITY 0x8
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#define ARB_PRIO_DMA_PRIORITY 0xC
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#define ARB_PRIO_UCQ_PRIORITY 0x10
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/*! AHB Gizmo registers. */
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#define AHB_ARBITRATION_PRIORITY_CTRL 0x8
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#define PRIORITY_CTRL_WEIGHT(x) (((x) & 7) << 29)
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