forked from CTCaer/hekate
bdk: usb: utilize apb relaxed clocks for init
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@ -1,7 +1,7 @@
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/*
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* Enhanced USB Device (EDCI) driver for Tegra X1
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*
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* Copyright (c) 2019-2023 CTCaer
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* Copyright (c) 2019-2024 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -355,9 +355,15 @@ int usb_device_init()
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if (usb_init_done)
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return USB_RES_OK;
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// Ease the stress to APB.
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bpmp_clk_rate_relaxed(true);
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// Initialize USB2 controller PHY.
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_usb_init_phy();
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// Restore OC.
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bpmp_clk_rate_relaxed(false);
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// AHB USB performance cfg.
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AHB_GIZMO(AHB_GIZMO_AHB_MEM) |= AHB_MEM_DONT_SPLIT_AHB_WR | AHB_MEM_ENB_FAST_REARBITRATE;
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AHB_GIZMO(AHB_GIZMO_USB) |= AHB_GIZMO_IMMEDIATE;
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@ -1,7 +1,7 @@
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/*
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* eXtensible USB Device driver (XDCI) for Tegra X1
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*
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* Copyright (c) 2020-2022 CTCaer
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* Copyright (c) 2020-2024 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -883,6 +883,9 @@ static void _xusbd_init_device_clocks()
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int xusb_device_init()
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{
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// Ease the stress to APB.
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bpmp_clk_rate_relaxed(true);
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// Disable USB2 device controller clocks.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_USBD);
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = BIT(CLK_L_USBD);
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@ -920,6 +923,9 @@ int xusb_device_init()
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// Initialize device clocks.
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_xusbd_init_device_clocks();
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// Restore OC.
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bpmp_clk_rate_relaxed(false);
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// Enable AHB redirect for access to IRAM for Event/EP ring buffers.
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mc_enable_ahb_redirect();
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