forked from CTCaer/hekate
bdk: sdmmc: rename ddr100 to the actual HS100 name
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CTCaer
parent
5e134ed54b
commit
502fc1ed50
@ -699,6 +699,7 @@ static clock_sdmmc_t _clock_sdmmc_table[4] = { 0 };
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#define SDMMC_CLOCK_SRC_PLLP_OUT0 0x0
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#define SDMMC_CLOCK_SRC_PLLC4_OUT2 0x3
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#define SDMMC_CLOCK_SRC_PLLC4_OUT0 0x7
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#define SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ 0x1
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static int _clock_sdmmc_config_clock_host(u32 *pclock, u32 id, u32 val)
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@ -716,79 +717,80 @@ static int _clock_sdmmc_config_clock_host(u32 *pclock, u32 id, u32 val)
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*pclock = 24728;
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divisor = 31; // 16.5 div.
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break;
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case 26000:
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*pclock = 25500;
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divisor = 30; // 16 div.
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break;
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case 50000:
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*pclock = 48000;
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divisor = 15; // 8.5 div.
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break;
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case 52000:
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*pclock = 51000;
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divisor = 14; // 8 div.
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break;
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case 81600: // Originally MMC_HS50 for GC FPGA at 40800 KHz, div 18 (real 10).
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case 82000:
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*pclock = 81600;
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divisor = 8; // 5 div.
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divisor = 8; // 5 div.
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break;
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case 100000:
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source = SDMMC_CLOCK_SRC_PLLC4_OUT2;
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*pclock = 99840;
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divisor = 2; // 2 div.
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break;
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case 164000:
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*pclock = 163200;
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divisor = 3; // 2.5 div.
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break;
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case 200000: // 240MHz evo+.
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case 200000:
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switch (id)
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{
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case SDMMC_1:
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source = SDMMC_CLOCK_SRC_PLLC4_OUT2;
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break;
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case SDMMC_2:
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source = SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ;
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break;
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case SDMMC_3:
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source = SDMMC_CLOCK_SRC_PLLC4_OUT2;
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break;
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case SDMMC_2:
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case SDMMC_4:
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source = SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ;
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source = SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ; // div is ignored.
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break;
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}
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*pclock = 199680;
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divisor = 0; // 1 div.
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break;
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default:
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*pclock = 24728;
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divisor = 31; // 16.5 div.
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}
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_clock_sdmmc_table[id].clock = val;
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_clock_sdmmc_table[id].real_clock = *pclock;
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// Enable PLLC4 if in use by any SDMMC.
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if (source)
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if (source != SDMMC_CLOCK_SRC_PLLP_OUT0)
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_clock_enable_pllc4(BIT(id));
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// Set SDMMC legacy timeout clock.
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_clock_sdmmc_config_legacy_tm();
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// Set SDMMC clock.
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u32 src_div = (source << 29) | divisor;
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switch (id)
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{
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case SDMMC_1:
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1) = (source << 29) | divisor;
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1) = src_div;
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break;
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case SDMMC_2:
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2) = (source << 29) | divisor;
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2) = src_div;
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break;
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case SDMMC_3:
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3) = (source << 29) | divisor;
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3) = src_div;
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break;
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case SDMMC_4:
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4) = (source << 29) | divisor;
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4) = src_div;
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break;
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}
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@ -818,51 +820,61 @@ void clock_sdmmc_get_card_clock_div(u32 *pclock, u16 *pdivisor, u32 type)
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// Get Card clock divisor.
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switch (type)
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{
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case SDHCI_TIMING_MMC_ID: // Actual IO Freq: 380.59 KHz.
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case SDHCI_TIMING_MMC_ID: // Actual card clock: 386.36 KHz.
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*pclock = 26000;
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*pdivisor = 66;
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break;
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case SDHCI_TIMING_MMC_LS26:
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*pclock = 26000;
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*pdivisor = 1;
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break;
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case SDHCI_TIMING_MMC_HS52:
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*pclock = 52000;
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*pdivisor = 1;
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break;
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case SDHCI_TIMING_MMC_HS200:
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case SDHCI_TIMING_MMC_HS400:
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case SDHCI_TIMING_UHS_SDR104:
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*pclock = 200000;
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*pdivisor = 1;
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break;
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case SDHCI_TIMING_SD_ID: // Actual IO Freq: 380.43 KHz.
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case SDHCI_TIMING_SD_ID: // Actual card clock: 386.38 KHz.
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*pclock = 25000;
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*pdivisor = 64;
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break;
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case SDHCI_TIMING_SD_DS12:
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case SDHCI_TIMING_UHS_SDR12:
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*pclock = 25000;
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*pdivisor = 1;
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break;
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case SDHCI_TIMING_SD_HS25:
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case SDHCI_TIMING_UHS_SDR25:
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*pclock = 50000;
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*pdivisor = 1;
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break;
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case SDHCI_TIMING_UHS_SDR50:
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*pclock = 100000;
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*pdivisor = 1;
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break;
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case SDHCI_TIMING_UHS_SDR82:
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*pclock = 164000;
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*pdivisor = 1;
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break;
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case SDHCI_TIMING_UHS_DDR50:
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*pclock = 81600; // Originally MMC_HS50 for GC FPGA at 40800 KHz, div 1.
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case SDHCI_TIMING_UHS_DDR50: // Actual card clock: 40.80 MHz.
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*pclock = 82000;
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*pdivisor = 2;
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break;
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case SDHCI_TIMING_MMC_DDR100: // Actual IO Freq: 99.84 MHz.
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case SDHCI_TIMING_MMC_HS100: // Actual card clock: 99.84 MHz.
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*pclock = 200000;
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*pdivisor = 2;
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break;
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@ -884,7 +896,8 @@ void clock_sdmmc_enable(u32 id, u32 val)
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_clock_sdmmc_config_clock_host(&clock, id, val);
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_clock_sdmmc_set_enable(id);
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_clock_sdmmc_is_reset(id);
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usleep((100000 + clock - 1) / clock);
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// Wait 100 cycles for reset and for clocks to stabilize.
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usleep((100 * 1000 + clock - 1) / clock);
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_clock_sdmmc_clear_reset(id);
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_clock_sdmmc_is_reset(id);
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}
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@ -1525,14 +1525,14 @@ int sdmmc_storage_init_gc(sdmmc_storage_t *storage, sdmmc_t *sdmmc)
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memset(storage, 0, sizeof(sdmmc_storage_t));
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storage->sdmmc = sdmmc;
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if (!sdmmc_init(sdmmc, SDMMC_2, SDMMC_POWER_1_8, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_DDR100))
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if (!sdmmc_init(sdmmc, SDMMC_2, SDMMC_POWER_1_8, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS100))
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return 0;
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DPRINTF("[GC] after init\n");
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// Wait 1ms + 10 clock cycles.
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usleep(1000 + (10 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock);
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if (!sdmmc_tuning_execute(storage->sdmmc, SDHCI_TIMING_MMC_DDR100, MMC_SEND_TUNING_BLOCK_HS200))
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if (!sdmmc_tuning_execute(storage->sdmmc, SDHCI_TIMING_MMC_HS100, MMC_SEND_TUNING_BLOCK_HS200))
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return 0;
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DPRINTF("[GC] after tuning\n");
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@ -332,7 +332,7 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
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case SDHCI_TIMING_UHS_SDR104:
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case SDHCI_TIMING_UHS_SDR82:
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case SDHCI_TIMING_UHS_DDR50:
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case SDHCI_TIMING_MMC_DDR100:
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case SDHCI_TIMING_MMC_HS100:
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sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | UHS_SDR104_BUS_SPEED;
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sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
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break;
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@ -673,7 +673,7 @@ int sdmmc_tuning_execute(sdmmc_t *sdmmc, u32 type, u32 cmd)
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case SDHCI_TIMING_UHS_SDR50:
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case SDHCI_TIMING_UHS_DDR50:
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case SDHCI_TIMING_MMC_DDR100:
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case SDHCI_TIMING_MMC_HS100:
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num_iter = 256;
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flag = (4 << 13); // 256 iterations.
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break;
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@ -261,7 +261,7 @@
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#define SDHCI_TIMING_UHS_DDR50 12
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// SDR104 with a 163.2MHz -> 81.6MHz clock.
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#define SDHCI_TIMING_UHS_SDR82 13 // GC FPGA. Obsolete and Repurposed. MMC_HS50 -> SDR82.
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#define SDHCI_TIMING_MMC_DDR100 14 // GC ASIC.
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#define SDHCI_TIMING_MMC_HS100 14 // GC ASIC.
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/*! SDMMC Low power features. */
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#define SDMMC_POWER_SAVE_DISABLE 0
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