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bdk: sdram: adjust sdmmc1 la for l4t

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CTCaer 2024-02-21 10:50:15 +02:00
parent 5f8814311e
commit 4131ff12d7
1 changed files with 18 additions and 6 deletions
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24
bdk/mem/minerva.c
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@ -27,10 +27,10 @@
#include <soc/t210.h> #include <soc/t210.h>
#include <utils/util.h> #include <utils/util.h>
#define LA_REGS_OFFSET_T210 0x1284 #define TABLE_FREQ_KHZ_OFFSET 0x40
#define LA_REGS_OFFSET_T210B01 0xFA4 #define TABLE_LA_REGS_T210_OFFSET 0x1284
#define TABLE_LA_REGS_T210B01_OFFSET 0xFA4
#define LA_SDMMC1_INDEX 6 #define LA_SDMMC1_INDEX 6
#define LA_SDMMC4_INDEX 9
extern volatile nyx_storage_t *nyx_str; extern volatile nyx_storage_t *nyx_str;
@ -148,10 +148,22 @@ void minerva_change_freq(minerva_freq_t freq)
void minerva_sdmmc_la_program(void *table, bool t210b01) void minerva_sdmmc_la_program(void *table, bool t210b01)
{ {
u32 *la_scale_regs = (u32 *)(table + (t210b01 ? LA_REGS_OFFSET_T210B01 : LA_REGS_OFFSET_T210)); u32 freq = *(u32 *)(table + TABLE_FREQ_KHZ_OFFSET);
u32 *la_scale_regs = (u32 *)(table + (t210b01 ? TABLE_LA_REGS_T210B01_OFFSET : TABLE_LA_REGS_T210_OFFSET));
// Promote SDMMC1 latency allowance to SDMMC4 (SD to eMMC). // Adjust SDMMC1 latency allowance.
la_scale_regs[LA_SDMMC1_INDEX] = la_scale_regs[LA_SDMMC4_INDEX]; switch (freq)
{
case 204000:
la_scale_regs[LA_SDMMC1_INDEX] = (la_scale_regs[LA_SDMMC1_INDEX] & 0xFF0000) | 75;
break;
case 408000:
la_scale_regs[LA_SDMMC1_INDEX] = (la_scale_regs[LA_SDMMC1_INDEX] & 0xFF0000) | 37;
break;
default:
la_scale_regs[LA_SDMMC1_INDEX] = (la_scale_regs[LA_SDMMC1_INDEX] & 0xFF0000) | 30;
break;
}
} }
void minerva_prep_boot_freq() void minerva_prep_boot_freq()