forked from CTCaer/hekate
bdk: hw init: do not touch audio clocks on t210b01
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@ -413,8 +413,7 @@ void hw_init()
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void hw_reinit_workaround(bool coreboot, u32 bl_magic)
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{
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// Disable BPMP max clock.
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bpmp_clk_rate_set(BPMP_CLK_NORMAL);
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bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210;
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#ifdef BDK_HW_EXTRA_DEINIT
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// Disable temperature sensor, touchscreen, 5V regulators, Joy-Con and VIC.
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@ -426,14 +425,20 @@ void hw_reinit_workaround(bool coreboot, u32 bl_magic)
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regulator_5v_disable(REGULATOR_5V_ALL);
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#endif
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// Flush/disable MMU cache and set DRAM clock to 204MHz.
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bpmp_mmu_disable();
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// set DRAM clock to 204MHz.
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minerva_change_freq(FREQ_204);
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nyx_str->mtc_cfg.init_done = 0;
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// Flush/disable MMU cache and scale down BPMP clock also.
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bpmp_mmu_disable();
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bpmp_clk_rate_set(BPMP_CLK_NORMAL);
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// Re-enable clocks to Audio Processing Engine as a workaround to hanging.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= BIT(CLK_V_AHUB);
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= BIT(CLK_Y_APE);
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if (tegra_t210)
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{
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= BIT(CLK_V_AHUB);
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= BIT(CLK_Y_APE);
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}
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// Do coreboot mitigations.
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if (coreboot)
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@ -461,7 +466,7 @@ void hw_reinit_workaround(bool coreboot, u32 bl_magic)
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display_backlight_brightness(brightness, 0);
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break;
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case BL_MAGIC_L4TLDR_SLD:
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// Do not disable backlight at all.
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// Do not disable display or backlight at all.
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break;
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default:
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display_end();
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